diff options
Diffstat (limited to 'src/southbridge/intel/ibexpeak/acpi')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/audio.asl | 36 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/globalnvs.asl | 301 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/irqlinks.asl | 493 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/lpc.asl | 248 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/pch.asl | 280 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/pcie.asl | 218 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/pcie_port.asl | 30 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/sata.asl | 83 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/sleepstates.asl | 27 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/smbus.asl | 242 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/usb.asl | 160 |
11 files changed, 0 insertions, 2118 deletions
diff --git a/src/southbridge/intel/ibexpeak/acpi/audio.asl b/src/southbridge/intel/ibexpeak/acpi/audio.asl deleted file mode 100644 index a4553289f2..0000000000 --- a/src/southbridge/intel/ibexpeak/acpi/audio.asl +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* Intel PCH HDA */ - -// Intel High Definition Audio (Azalia) 0:1b.0 - -Device (HDEF) -{ - Name (_ADR, 0x001b0000) - - // Power Resources for Wake - Name (_PRW, Package(){ - 13, // Bit 13 of GPE - 4 // Can wake from S4 state. - }) -} - diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl deleted file mode 100644 index 99edc317cf..0000000000 --- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl +++ /dev/null @@ -1,301 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* Global Variables */ - -Name(\PICM, 0) // IOAPIC/8259 -Name(\DSEN, 1) // Display Output Switching Enable - -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - - -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - Offset (0x00), - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - /* Thermal policy */ - Offset (0x11), - TLVL, 8, // 0x11 - Throttle Level Limit - FLVL, 8, // 0x12 - Current FAN Level - TCRT, 8, // 0x13 - Critical Threshold - TPSV, 8, // 0x14 - Passive Threshold - TMAX, 8, // 0x15 - CPU Tj_max - F0OF, 8, // 0x16 - FAN 0 OFF Threshold - F0ON, 8, // 0x17 - FAN 0 ON Threshold - F0PW, 8, // 0x18 - FAN 0 PWM value - F1OF, 8, // 0x19 - FAN 1 OFF Threshold - F1ON, 8, // 0x1a - FAN 1 ON Threshold - F1PW, 8, // 0x1b - FAN 1 PWM value - F2OF, 8, // 0x1c - FAN 2 OFF Threshold - F2ON, 8, // 0x1d - FAN 2 ON Threshold - F2PW, 8, // 0x1e - FAN 2 PWM value - F3OF, 8, // 0x1f - FAN 3 OFF Threshold - F3ON, 8, // 0x20 - FAN 3 ON Threshold - F3PW, 8, // 0x21 - FAN 3 PWM value - F4OF, 8, // 0x22 - FAN 4 OFF Threshold - F4ON, 8, // 0x23 - FAN 4 ON Threshold - F4PW, 8, // 0x24 - FAN 4 PWM value - TMPS, 8, // 0x25 - Temperature Sensor ID - /* Processor Identification */ - Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable - PCP0, 8, // 0x2a - PDC CPU/CORE 0 - PCP1, 8, // 0x2b - PDC CPU/CORE 1 - PPCM, 8, // 0x2c - Max. PPC state - PCNT, 8, // 0x2d - Processor count - /* Super I/O & CMOS config */ - Offset (0x32), - NATP, 8, // 0x32 - - S5U0, 8, // 0x33 - Enable USB0 in S5 - S5U1, 8, // 0x34 - Enable USB1 in S5 - S3U0, 8, // 0x35 - Enable USB0 in S3 - S3U1, 8, // 0x36 - Enable USB1 in S3 - S33G, 8, // 0x37 - Enable 3G in S3 - CMEM, 32, // 0x38 - CBMEM TOC - /* Integrated Graphics Device */ - Offset (0x3c), - IGDS, 8, // 0x3c - IGD state (primary = 1) - TLST, 8, // 0x3d - Display Toggle List pointer - CADL, 8, // 0x3e - Currently Attached Devices List - PADL, 8, // 0x3f - Previously Attached Devices List - CSTE, 16, // 0x40 - Current display state - NSTE, 16, // 0x42 - Next display state - SSTE, 16, // 0x44 - Set display state - Offset (0x46), - NDID, 8, // 0x46 - Number of Device IDs - DID1, 32, // 0x47 - Device ID 1 - DID2, 32, // 0x4b - Device ID 2 - DID3, 32, // 0x4f - Device ID 3 - DID4, 32, // 0x53 - Device ID 4 - DID5, 32, // 0x57 - Device ID 5 - /* Backlight Control */ - Offset (0x64), - BLCS, 8, // 0x64 - Backlight control possible? - BRTL, 8, // 0x65 - Brightness Level - ODDS, 8, // 0x66 - /* Ambient Light Sensors */ - Offset (0x6e), - ALSE, 8, // 0x6e - ALS enable - ALAF, 8, // 0x6f - Ambient light adjustment factor - LLOW, 8, // 0x70 - LUX Low - LHIH, 8, // 0x71 - LUX High - /* EMA */ - Offset (0x78), - EMAE, 8, // 0x78 - EMA enable - EMAP, 16, // 0x79 - EMA pointer - EMAL, 16, // 0x7b - EMA length - /* MEF */ - Offset (0x82), - MEFE, 8, // 0x82 - MEF enable - /* TPM support */ - Offset (0x8c), - TPMP, 8, // 0x8c - TPM - TPME, 8, // 0x8d - TPM enable - /* SATA */ - Offset (0x96), - GTF0, 56, // 0x96 - GTF task file buffer for port 0 - GTF1, 56, // 0x9d - GTF task file buffer for port 1 - GTF2, 56, // 0xa4 - GTF task file buffer for port 2 - IDEM, 8, // 0xab - IDE mode (compatible / enhanced) - IDET, 8, // 0xac - IDE - /* XHCI */ - Offset (0xb2), - XHCI, 8, - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> -} - -/* Set flag to enable USB charging in S3 */ -Method (S3UE) -{ - Store (One, \S3U0) - Store (One, \S3U1) -} - -/* Set flag to disable USB charging in S3 */ -Method (S3UD) -{ - Store (Zero, \S3U0) - Store (Zero, \S3U1) -} - -/* Set flag to enable USB charging in S5 */ -Method (S5UE) -{ - Store (One, \S5U0) - Store (One, \S5U1) -} - -/* Set flag to disable USB charging in S5 */ -Method (S5UD) -{ - Store (Zero, \S5U0) - Store (Zero, \S5U1) -} - -/* Set flag to enable 3G module in S3 */ -Method (S3GE) -{ - Store (One, \S33G) -} - -/* Set flag to disable 3G module in S3 */ -Method (S3GD) -{ - Store (Zero, \S33G) -} - -/* Set XHCI Mode enable */ -Method (XHCE) -{ - Store (One, \XHCI) -} - -/* Set XHCI Mode disable */ -Method (XHCD) -{ - Store (Zero, \XHCI) -} -External (\_TZ.THRM) -External (\_TZ.SKIN) - -Method (TZUP) -{ - /* Update Primary Thermal Zone */ - If (CondRefOf (\_TZ.THRM, Local0)) { - Notify (\_TZ.THRM, 0x81) - } - - /* Update Secondary Thermal Zone */ - If (CondRefOf (\_TZ.SKIN, Local0)) { - Notify (\_TZ.SKIN, 0x81) - } -} - -/* Update Fan 0 thresholds */ -Method (F0UT, 2) -{ - Store (Arg0, \F0OF) - Store (Arg1, \F0ON) - TZUP () -} - -/* Update Fan 1 thresholds */ -Method (F1UT, 2) -{ - Store (Arg0, \F1OF) - Store (Arg1, \F1ON) - TZUP () -} - -/* Update Fan 2 thresholds */ -Method (F2UT, 2) -{ - Store (Arg0, \F2OF) - Store (Arg1, \F2ON) - TZUP () -} - -/* Update Fan 3 thresholds */ -Method (F3UT, 2) -{ - Store (Arg0, \F3OF) - Store (Arg1, \F3ON) - TZUP () -} - -/* Update Fan 4 thresholds */ -Method (F4UT, 2) -{ - Store (Arg0, \F4OF) - Store (Arg1, \F4ON) - TZUP () -} - -/* Update Temperature Sensor ID */ -Method (TMPU, 1) -{ - Store (Arg0, \TMPS) - TZUP () -} diff --git a/src/southbridge/intel/ibexpeak/acpi/irqlinks.asl b/src/southbridge/intel/ibexpeak/acpi/irqlinks.asl deleted file mode 100644 index 5fcee45f29..0000000000 --- a/src/southbridge/intel/ibexpeak/acpi/irqlinks.asl +++ /dev/null @@ -1,493 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Device (LNKA) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 1) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTA) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLA, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLA, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) - - Return (RTLA) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTA) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTA, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKB) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 2) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTB) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLB, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLB, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) - - Return (RTLB) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTB) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTB, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKC) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 3) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLC, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLC, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) - - Return (RTLC) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTC) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTC, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKD) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 4) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTD) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLD, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLD, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) - - Return (RTLD) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTD) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTD, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKE) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 5) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTE) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLE, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLE, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) - - Return (RTLE) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTE) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTE, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKF) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 6) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTF) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLF, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLF, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) - - Return (RTLF) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTF) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTF, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKG) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 7) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTG) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLG, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLG, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) - - Return (RTLG) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTG) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTG, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKH) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 8) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTH) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLH, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLH, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) - - Return (RTLH) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTH) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTH, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - diff --git a/src/southbridge/intel/ibexpeak/acpi/lpc.asl b/src/southbridge/intel/ibexpeak/acpi/lpc.asl deleted file mode 100644 index cc59850ec4..0000000000 --- a/src/southbridge/intel/ibexpeak/acpi/lpc.asl +++ /dev/null @@ -1,248 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// Intel LPC Bus Device - 0:1f.0 - -Device (LPCB) -{ - Name(_ADR, 0x001f0000) - - OperationRegion(LPC0, PCI_Config, 0x00, 0x100) - Field (LPC0, AnyAcc, NoLock, Preserve) - { - Offset (0x40), - PMBS, 16, // PMBASE - Offset (0x60), // Interrupt Routing Registers - PRTA, 8, - PRTB, 8, - PRTC, 8, - PRTD, 8, - Offset (0x68), - PRTE, 8, - PRTF, 8, - PRTG, 8, - PRTH, 8, - - Offset (0x80), // IO Decode Ranges - IOD0, 8, - IOD1, 8, - - Offset (0xb8), // GPIO Routing Control - GR00, 2, - GR01, 2, - GR02, 2, - GR03, 2, - GR04, 2, - GR05, 2, - GR06, 2, - GR07, 2, - GR08, 2, - GR09, 2, - GR10, 2, - GR11, 2, - GR12, 2, - GR13, 2, - GR14, 2, - GR15, 2, - - Offset (0xf0), // RCBA - RCEN, 1, - , 13, - RCBA, 18, - } - - #include "irqlinks.asl" - - #include "acpi/ec.asl" - - Device (DMAC) // DMA Controller - { - Name(_HID, EISAID("PNP0200")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x00, 0x00, 0x01, 0x20) - IO (Decode16, 0x81, 0x81, 0x01, 0x11) - IO (Decode16, 0x93, 0x93, 0x01, 0x0d) - IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) - DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } - }) - } - - Device (FWH) // Firmware Hub - { - Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID("PNP0103")) - Name (_CID, 0x010CD041) - - Name(BUF0, ResourceTemplate() - { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) - }) - - Method (_STA, 0) // Device Status - { - If (HPTE) { - // Note: Ancient versions of Windows don't want - // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { - Return (0xf) // Enable and show device - } Else { - Return (0xb) // Enable and don't show device - } - } - - Return (0x0) // Not enabled, don't show. - } - - Method (_CRS, 0, Serialized) // Current resources - { - If (HPTE) { - CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) - } - - If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) - } - - If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) - } - } - - Return (BUF0) - } - } - - Device(PIC) // 8259 Interrupt Controller - { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device(MATH) // FPU - { - Name (_HID, EISAID("PNP0C04")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) - IRQNoFlags() { 13 } - }) - } - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 2) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap - IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI - IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO - }) - } - - Device (RTC) // Real Time Clock - { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } - }) - } - - Device (TIMR) // Intel 8254 timer - { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} - }) - } - - #include "acpi/superio.asl" - -#ifdef ENABLE_TPM - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - IRQ (Edge, Activehigh, Exclusive) { 6 } - }) - } -#endif -} diff --git a/src/southbridge/intel/ibexpeak/acpi/pch.asl b/src/southbridge/intel/ibexpeak/acpi/pch.asl deleted file mode 100644 index 2f75fdc3f7..0000000000 --- a/src/southbridge/intel/ibexpeak/acpi/pch.asl +++ /dev/null @@ -1,280 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* Intel Cougar Point PCH support */ - -Scope(\) -{ - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) - { - Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 - } - - // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) - OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) - Field(PMIO, ByteAcc, NoLock, Preserve) - { - Offset(0x20), // GPE0_STS - , 16, - GS00, 1, // GPIO00 SCI/Wake Status - GS01, 1, // GPIO01 SCI/Wake Status - GS02, 1, // GPIO02 SCI/Wake Status - GS03, 1, // GPIO03 SCI/Wake Status - GS04, 1, // GPIO04 SCI/Wake Status - GS05, 1, // GPIO05 SCI/Wake Status - GS06, 1, // GPIO06 SCI/Wake Status - GS07, 1, // GPIO07 SCI/Wake Status - GS08, 1, // GPIO08 SCI/Wake Status - GS09, 1, // GPIO09 SCI/Wake Status - GS10, 1, // GPIO10 SCI/Wake Status - GS11, 1, // GPIO11 SCI/Wake Status - GS12, 1, // GPIO12 SCI/Wake Status - GS13, 1, // GPIO13 SCI/Wake Status - GS14, 1, // GPIO14 SCI/Wake Status - GS15, 1, // GPIO15 SCI/Wake Status - Offset(0x28), // GPE0_EN - , 16, - GE00, 1, // GPIO00 SCI/Wake Enable - GE01, 1, // GPIO01 SCI/Wake Enable - GE02, 1, // GPIO02 SCI/Wake Enable - GE03, 1, // GPIO03 SCI/Wake Enable - GE04, 1, // GPIO04 SCI/Wake Enable - GE05, 1, // GPIO05 SCI/Wake Enable - GE06, 1, // GPIO06 SCI/Wake Enable - GE07, 1, // GPIO07 SCI/Wake Enable - GE08, 1, // GPIO08 SCI/Wake Enable - GE09, 1, // GPIO09 SCI/Wake Enable - GE10, 1, // GPIO10 SCI/Wake Enable - GE11, 1, // GPIO11 SCI/Wake Enable - GE12, 1, // GPIO12 SCI/Wake Enable - GE13, 1, // GPIO13 SCI/Wake Enable - GE14, 1, // GPIO14 SCI/Wake Enable - GE15, 1, // GPIO15 SCI/Wake Enable - Offset(0x42), // General Purpose Control - , 1, // skip 1 bit - GPEC, 1, // SWGPE_CTRL - } - - // GPIO IO mapped registers (0x1f.0 reg 0x48.l) - OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) - Field(GPIO, ByteAcc, NoLock, Preserve) - { - Offset(0x00), // GPIO Use Select - GU00, 8, - GU01, 8, - GU02, 8, - GU03, 8, - Offset(0x04), // GPIO IO Select - GIO0, 8, - GIO1, 8, - GIO2, 8, - GIO3, 8, - Offset(0x0c), // GPIO Level - GL00, 1, - GP01, 1, - GP02, 1, - GP0e, 1, - GP04, 1, - GP05, 1, - GP06, 1, - GP07, 1, - GP08, 1, - GP09, 1, - GP10, 1, - GP11, 1, - GP12, 1, - GP13, 1, - GP14, 1, - GP15, 1, - GP16, 1, - GP17, 1, - GP18, 1, - GP19, 1, - GP20, 1, - GP21, 1, - GP22, 1, - GP23, 1, - GP24, 1, - GP25, 1, - GP26, 1, - GP27, 1, - GP28, 1, - GP29, 1, - GP30, 1, - GP31, 1, - Offset(0x18), // GPIO Blink - GB00, 8, - GB01, 8, - GB02, 8, - GB03, 8, - Offset(0x2c), // GPIO Invert - GIV0, 8, - GIV1, 8, - GIV2, 8, - GIV3, 8, - Offset(0x30), // GPIO Use Select 2 - GU04, 8, - GU05, 8, - GU06, 8, - GU07, 8, - Offset(0x34), // GPIO IO Select 2 - GIO4, 8, - GIO5, 8, - GIO6, 8, - GIO7, 8, - Offset(0x38), // GPIO Level 2 - GP32, 1, - GP33, 1, - GP34, 1, - GP35, 1, - GP36, 1, - GP37, 1, - GP38, 1, - GP39, 1, - GP40, 1, - GP41, 1, - GP42, 1, - GP43, 1, - GP44, 1, - GP45, 1, - GP46, 1, - GP47, 1, - GP48, 1, - GP49, 1, - GP50, 1, - GP51, 1, - GP52, 1, - GP53, 1, - GP54, 1, - GP55, 1, - GP56, 1, - GP57, 1, - GP58, 1, - GP59, 1, - GP60, 1, - GP61, 1, - GP62, 1, - GP63, 1, - Offset(0x40), // GPIO Use Select 3 - GU08, 8, - GU09, 4, - Offset(0x44), // GPIO IO Select 3 - GIO8, 8, - GIO9, 4, - Offset(0x48), // GPIO Level 3 - GP64, 1, - GP65, 1, - GP66, 1, - GP67, 1, - GP68, 1, - GP69, 1, - GP70, 1, - GP71, 1, - GP72, 1, - GP73, 1, - GP74, 1, - GP75, 1, - } - - - // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) - Field(RCRB, DWordAcc, Lock, Preserve) - { - Offset(0x0000), // Backbone - Offset(0x1000), // Chipset - Offset(0x3000), // Legacy Configuration Registers - Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select - , 5, - HPTE, 1, // Address Enable - Offset(0x3418), // FD (Function Disable) - , 1, // Reserved - PCID, 1, // PCI bridge disable - SA1D, 1, // SATA1 disable - SMBD, 1, // SMBUS disable - HDAD, 1, // Azalia disable - , 8, // Reserved - EH2D, 1, // EHCI #2 disable - LPBD, 1, // LPC bridge disable - EH1D, 1, // EHCI #1 disable - RP1D, 1, // Root Port 1 disable - RP2D, 1, // Root Port 2 disable - RP3D, 1, // Root Port 3 disable - RP4D, 1, // Root Port 4 disable - RP5D, 1, // Root Port 5 disable - RP6D, 1, // Root Port 6 disable - RP7D, 1, // Root Port 7 disable - RP8D, 1, // Root Port 8 disable - TTRD, 1, // Thermal sensor registers disable - SA2D, 1, // SATA2 disable - Offset(0x3428), // FD2 (Function Disable 2) - BDFD, 1, // Display BDF - ME1D, 1, // ME Interface 1 disable - ME2D, 1, // ME Interface 2 disable - IDRD, 1, // IDE redirect disable - KTCT, 1, // Keyboard Text redirect disable - } -} - -// High Definition Audio (Azalia) 0:1b.0 -#include "audio.asl" - -// PCI Express Ports 0:1c.x -#include "pcie.asl" - -// USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0 -#include "usb.asl" - -// LPC Bridge 0:1f.0 -#include "lpc.asl" - -// SATA 0:1f.2, 0:1f.5 -#include "sata.asl" - -// SMBus 0:1f.3 -#include "smbus.asl" - -Method (_OSC, 4) -{ - /* Check for XHCI */ - If (LEqual (Arg0, ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) - { - Return (^XHC.POSC(Arg1, Arg2, Arg3)) - } - - /* Check for PCIe */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - - /* Else Return Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - -} diff --git a/src/southbridge/intel/ibexpeak/acpi/pcie.asl b/src/southbridge/intel/ibexpeak/acpi/pcie.asl deleted file mode 100644 index 934cf782e9..0000000000 --- a/src/southbridge/intel/ibexpeak/acpi/pcie.asl +++ /dev/null @@ -1,218 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* Intel 6/7 Series PCH PCIe support */ - -// PCI Express Ports - -Method (IRQM, 1, Serialized) { - - /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) - - /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } }) - - /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } }) - - /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } }) - - Switch (ToInteger (Arg0)) { - /* PCIe Root Port 1 and 5 */ - Case (Package() { 1, 5 }) { - If (PICM) { - Return (IQAA) - } Else { - Return (IQAP) - } - } - - /* PCIe Root Port 2 and 6 */ - Case (Package() { 2, 6 }) { - If (PICM) { - Return (IQBA) - } Else { - Return (IQBP) - } - } - - /* PCIe Root Port 3 and 7 */ - Case (Package() { 3, 7 }) { - If (PICM) { - Return (IQCA) - } Else { - Return (IQCP) - } - } - - /* PCIe Root Port 4 and 8 */ - Case (Package() { 4, 8 }) { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - - Default { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - } -} - -Device (RP01) -{ - Name (_ADR, 0x001c0000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001c0001) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001c0002) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001c0003) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001c0004) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001c0005) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001c0006) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001c0007) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/southbridge/intel/ibexpeak/acpi/pcie_port.asl b/src/southbridge/intel/ibexpeak/acpi/pcie_port.asl deleted file mode 100644 index fedd9c97c6..0000000000 --- a/src/southbridge/intel/ibexpeak/acpi/pcie_port.asl +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number -} diff --git a/src/southbridge/intel/ibexpeak/acpi/sata.asl b/src/southbridge/intel/ibexpeak/acpi/sata.asl deleted file mode 100644 index e0c336ac5d..0000000000 --- a/src/southbridge/intel/ibexpeak/acpi/sata.asl +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// Intel SATA Controller 0:1f.2 - -// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily -// pluggable - -Device (SATA) -{ - Name (_ADR, 0x001f0002) - - Device (PRID) - { - Name (_ADR, 0) - - // Get Timing Mode - Method (_GTM) - { - Name(PBUF, Buffer(20) { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00 }) - - CreateDwordField (PBUF, 0, PIO0) - CreateDwordField (PBUF, 4, DMA0) - CreateDwordField (PBUF, 8, PIO1) - CreateDwordField (PBUF, 12, DMA1) - CreateDwordField (PBUF, 16, FLAG) - - // TODO fill return structure - - Return (PBUF) - } - - // Set Timing Mode - Method (_STM, 3) - { - CreateDwordField (Arg0, 0, PIO0) - CreateDwordField (Arg0, 4, DMA0) - CreateDwordField (Arg0, 8, PIO1) - CreateDwordField (Arg0, 12, DMA1) - CreateDwordField (Arg0, 16, FLAG) - - // TODO: Do the deed - } - - Device (DSK0) - { - Name (_ADR, 0) - // TODO: _RMV ? - // TODO: _GTF ? - } - - Device (DSK1) - { - Name (_ADR, 1) - - // TODO: _RMV ? - // TODO: _GTF ? - } - - } -} - diff --git a/src/southbridge/intel/ibexpeak/acpi/sleepstates.asl b/src/southbridge/intel/ibexpeak/acpi/sleepstates.asl deleted file mode 100644 index 06bfcb6a58..0000000000 --- a/src/southbridge/intel/ibexpeak/acpi/sleepstates.asl +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) -Name(\_S3, Package(){0x5,0x5,0x0,0x0}) -Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -Name(\_S5, Package(){0x7,0x7,0x0,0x0}) - diff --git a/src/southbridge/intel/ibexpeak/acpi/smbus.asl b/src/southbridge/intel/ibexpeak/acpi/smbus.asl deleted file mode 100644 index 4409308325..0000000000 --- a/src/southbridge/intel/ibexpeak/acpi/smbus.asl +++ /dev/null @@ -1,242 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// Intel SMBus Controller 0:1f.3 - -Device (SBUS) -{ - Name (_ADR, 0x001f0003) - -#ifdef ENABLE_SMBUS_METHODS - OperationRegion (SMBP, PCI_Config, 0x00, 0x100) - Field(SMBP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), - , 2, - I2CE, 1 - } - - OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20) - Field (SMBI, ByteAcc, NoLock, Preserve) - { - HSTS, 8, // Host Status - , 8, - HCNT, 8, // Host Control - HCMD, 8, // Host Command - TXSA, 8, // Transmit Slave Address - DAT0, 8, // Host Data 0 - DAT1, 8, // Host Data 1 - HBDB, 8, // Host Block Data Byte - PECK, 8, // Packet Error Check - RXSA, 8, // Receive Slave Address - RXDA, 16, // Receive Slave Data - AUXS, 8, // Auxiliary Status - AUXC, 8, // Auxiliary Control - SLPC, 8, // SMLink Pin Control - SBPC, 8, // SMBus Pin Control - SSTS, 8, // Slave Status - SCMD, 8, // Slave Command - NADR, 8, // Notify Device Address - NDLB, 8, // Notify Data Low Byte - NDLH, 8, // Notify Data High Byte - } - - // Kill all SMBus communication - Method (KILL, 0, Serialized) - { - Or (HCNT, 0x02, HCNT) // Send Kill - Or (HSTS, 0xff, HSTS) // Clean Status - } - - // Check if last operation completed - // return Failure = 0, Success = 1 - Method (CMPL, 0, Serialized) - { - Store (4000, Local0) // Timeout 200ms in 50us steps - While (Local0) { - If (And(HSTS, 0x02)) { // Completion Status? - Return (1) // Operation Completed - } Else { - Stall (50) - Decrement (Local0) - If (LEqual(Local0, 0)) { - KILL() - } - } - } - - Return (0) // Failure - } - - - // Wait for SMBus to become ready - Method (SRDY, 0, Serialized) - { - Store (200, Local0) // Timeout 200ms - While (Local0) { - If (And(HSTS, 0x40)) { // IN_USE? - Sleep(1) // Wait 1ms - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - Return (1) - } - } Else { - Store (0, Local0) // We're ready - } - } - - Store (4000, Local0) // Timeout 200ms (50us * 4000) - While (Local0) { - If (And (HSTS, 0x01)) { // Host Busy? - Stall(50) // Wait 50us - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - KILL() - } - } Else { - Return (0) // Success - } - } - - Return (1) // Failure - } - - // SMBus Send Byte - // Arg0: Address - // Arg1: Data - // Return: 1 = Success, 0=Failure - - Method (SSXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Data - - Store (0x48, HCNT) // Start + Byte Data Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Receive Byte - // Arg0: Address - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - - Store (0x44, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } - - - // SMBus Write Byte - // Arg0: Address - // Arg1: Command - // Arg2: Data - // Return: 1 = Success, 0=Failure - - Method (SWRB, 3, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Command - Store (Arg2, DAT0) // Write Data - - Store (0x48, HCNT) // Start + Byte Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Read Byte - // Arg0: Address - // Arg1: Command - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRDB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - Store (Arg1, HCMD) // Command - - Store (0x48, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } -#endif -} - diff --git a/src/southbridge/intel/ibexpeak/acpi/usb.asl b/src/southbridge/intel/ibexpeak/acpi/usb.asl deleted file mode 100644 index f19d3685ae..0000000000 --- a/src/southbridge/intel/ibexpeak/acpi/usb.asl +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* Intel Cougar Point USB support */ - -// EHCI Controller 0:1d.0 - -Device (EHC1) -{ - Name(_ADR, 0x001d0000) - - Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake - - // Leave USB ports on for to allow Wake from USB - - Method(_S3D,0) // Highest D State in S3 State - { - Return (2) - } - - Method(_S4D,0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0x00000000) - - // How many are there? - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - Device (PRT5) { Name (_ADR, 5) } // USB Port 4 - Device (PRT6) { Name (_ADR, 6) } // USB Port 5 - } -} - -// EHCI #2 Controller 0:1a.0 - -Device (EHC2) -{ - Name(_ADR, 0x001a0000) - - Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake - - // Leave USB ports on for to allow Wake from USB - - Method(_S3D,0) // Highest D State in S3 State - { - Return (2) - } - - Method(_S4D,0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0x00000000) - - // How many are there? - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - Device (PRT5) { Name (_ADR, 5) } // USB Port 4 - Device (PRT6) { Name (_ADR, 6) } // USB Port 5 - } -} - -Device (XHC) -{ - Name(_ADR, 0x00140000) - OperationRegion(XDEV, PCI_Config, 0, 256) - Field(XDEV, DWordAcc, NoLock, Preserve) - { - Offset(0xD0), - X2PR, 32, // XUSB2PR - PRM2, 32, // XUSB2PRM - SSEN, 32, // USB3_PSSEN - RPM3, 32, // USB3PRM - XPRT, 32, // XHCI Ports - } - - Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake - - Method(POSC,3,Serialized) - { - // Create DWord field from the Capabilities Buffer - CreateDWordField(Arg2,0,CDW1) - - // Check revision - If(LNotEqual(Arg1,One)) { - // Set unknown revision bit - Or(CDW1,0x8,CDW1) - } - - // Set failure if xHCI is disabled by coreboot - If(LEqual(XHCI, 0)) { - Or(CDW1,0x2,CDW1) - } - - // Query flag clear and xHCI in auto mode - If(LAnd(LNot(And(CDW1,0x1)),LOr(LEqual(XHCI ,2), LEqual(XHCI ,3)))) { - Store ("XHCI Switch", Debug) - Store(Zero, Local0) - And(XPRT, 0x3, Local0) - If(LOr(LEqual(Local0, 0), LEqual(Local0, 1))) { - Store(0xF, Local1) - } - ElseIf(LEqual(Local0, 2)) { - Store(0x3, Local1) - } - ElseIf(LEqual(Local0, 3)) { - Store(Zero, Local1) - } - And(RPM3, 0xFFFFFFF0, Local0) - Or(Local0, Local1, RPM3) - And(PRM2, 0xFFFFFFF0, Local0) - Or(Local0, Local1, PRM2) - And(SSEN, 0xFFFFFFF0, Local0) - Or(Local0, Local1, SSEN) - And(X2PR, 0xFFFFFFF0, Local0) - Or(Local0, Local1, X2PR) - } - Return(Arg2) - } - - // Leave USB ports on for to allow Wake from USB - Method(_S3D,0) // Highest D State in S3 State - { - Return (2) - } - - Method(_S4D,0) // Highest D State in S4 State - { - Return (2) - } -} |