5 files changed, 0 insertions, 145 deletions
diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h
deleted file mode 100644
index c8adb0eb95..0000000000
--- a/src/southbridge/intel/i82870/82870.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* for io APIC 1461 */
-#define MBAR		0x10
-#define ABAR		0x40
-
-/* for pci bridge  1460 */
-#define MTT		0x042
-#define HCCR		0x0f0
-#define ACNF		0x0e0
-#define STRP		0x44		// Strap status register
-
-#define STRP_EN133	0x0001		// 133 MHz-capable (Px_133EN)
-#define STRP_HPCAP	0x0002		// Hot-plug capable (Hx_SLOT zero/nonzero)
-
-#define ACNF_SYNCPH	0x0010		// PCI(-X) input clock is synchronous to hub input clock
diff --git a/src/southbridge/intel/i82870/Kconfig b/src/southbridge/intel/i82870/Kconfig
deleted file mode 100644
index b56113b8e2..0000000000
--- a/src/southbridge/intel/i82870/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-config SOUTHBRIDGE_INTEL_I82870
-	bool
diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc
deleted file mode 100644
index d6ae171926..0000000000
--- a/src/southbridge/intel/i82870/Makefile.inc
+++ /dev/null
@@ -1,6 +0,0 @@
-ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y)
-
-ramstage-y += ioapic.c
-ramstage-y += pcibridge.c
-
-endif
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
deleted file mode 100644
index 65fecd10f8..0000000000
--- a/src/southbridge/intel/i82870/ioapic.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <assert.h>
-#include "82870.h"
-
-static int num_p64h2_ioapics = 0;
-
-static void p64h2_ioapic_enable(struct device *dev)
-{
-	/* We have to enable MEM and Bus Master for IOAPIC */
-	uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-
-	pci_write_config16(dev, PCI_COMMAND, command);
-}
-
-/**
- * Configure one of the IOAPICs in a P64H2.
- *
- * Note that a PCI bus scan will detect both IOAPICs, so this function
- * will be called twice for each P64H2 in the system.
- *
- * @param dev PCI bus/device/function of P64H2 IOAPIC.
- *            NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.
- */
-static void p64h2_ioapic_init(struct device *dev)
-{
-	uint32_t memoryBase;
-	int apic_index, apic_id;
-
-	apic_index = num_p64h2_ioapics;
-	num_p64h2_ioapics++;
-
-	// A note on IOAPIC addresses:
-	//  0 and 1 are used for the local APICs of the dual virtual
-	//  (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
-	//  6 and 7 are used for the local APICs of the dual virtual
-	//  (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
-	//  2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
-
-	// Map APIC index into APIC ID
-	// IDs 3, 4, 5, and 8+ are available (see above note)
-
-	if (apic_index < 3)
-		apic_id = apic_index + 3;
-	else
-		apic_id = apic_index + 5;
-
-	ASSERT(apic_id < 16);       // ID is only 4 bits
-
-	// Read the MBAR address for setting up the IOAPIC in memory space
-	// NOTE: this address was assigned during enumeration of the bus
-
-	memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-
-	set_ioapic_id((void *)memoryBase, apic_id);
-
-	// Use Processor System Bus to deliver interrupts
-	ioapic_set_boot_config((void *)memoryBase, true);
-}
-
-static struct device_operations ioapic_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init     = p64h2_ioapic_init,
-	.enable   = p64h2_ioapic_enable,
-};
-
-static const struct pci_driver ioapic_driver __pci_driver = {
-	.ops    = &ioapic_ops,
-	.vendor = PCI_VID_INTEL,
-	.device = PCI_DID_INTEL_82870_1E0,
-
-};
diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c
deleted file mode 100644
index 00bf6bb1cf..0000000000
--- a/src/southbridge/intel/i82870/pcibridge.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "82870.h"
-
-static void p64h2_pcix_init(struct device *dev)
-{
-	u32 dword;
-	u8 byte;
-
-	/* The purpose of changes to HCCR, ACNF, and MTT is to speed
-	 * up the PCI bus for cards having high speed transfers.
-	 */
-	dword = 0xc2040002;
-	pci_write_config32(dev, HCCR, dword);
-	dword = 0x0000c3bf;
-	pci_write_config32(dev, ACNF, dword);
-	byte = 0x08;
-	pci_write_config8(dev, MTT, byte);
-
-}
-static struct device_operations pcix_ops  = {
-	.read_resources   = pci_bus_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init             = p64h2_pcix_init,
-	.scan_bus         = pci_scan_bridge,
-	.reset_bus        = pci_bus_reset,
-};
-
-static const struct pci_driver pcix_driver __pci_driver = {
-	.ops    = &pcix_ops,
-	.vendor = PCI_VID_INTEL,
-	.device = PCI_DID_INTEL_82870_1F0,
-};
-
-struct chip_operations southbridge_intel_i82870_ops = {
-	CHIP_NAME("Intel 82870")
-};