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-rw-r--r--src/southbridge/intel/i82801jx/Makefile.inc1
-rw-r--r--src/southbridge/intel/i82801jx/chip.h6
-rw-r--r--src/southbridge/intel/i82801jx/early_init.c54
-rw-r--r--src/southbridge/intel/i82801jx/i82801jx.h1
4 files changed, 62 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc
index 02da8146e9..30ed351970 100644
--- a/src/southbridge/intel/i82801jx/Makefile.inc
+++ b/src/southbridge/intel/i82801jx/Makefile.inc
@@ -31,6 +31,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
smm-y += smihandler.c
+romstage-y += early_init.c
romstage-y += early_smbus.c
endif
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h
index 1712b8162c..e4c68fb95a 100644
--- a/src/southbridge/intel/i82801jx/chip.h
+++ b/src/southbridge/intel/i82801jx/chip.h
@@ -78,6 +78,12 @@ struct southbridge_intel_i82801jx_config {
} pcie_power_limits[6];
uint8_t pcie_hotplug_map[8];
+
+ /* Additional LPC IO decode ranges */
+ uint32_t gen1_dec;
+ uint32_t gen2_dec;
+ uint32_t gen3_dec;
+ uint32_t gen4_dec;
};
#endif /* SOUTHBRIDGE_INTEL_I82801JX_CHIP_H */
diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c
new file mode 100644
index 0000000000..9d40cf2d27
--- /dev/null
+++ b/src/southbridge/intel/i82801jx/early_init.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_ops.h>
+#include "i82801jx.h"
+#include "chip.h"
+
+void i82801jx_lpc_setup(void)
+{
+ const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
+ const struct device *dev = pcidev_on_root(0x1f, 0);
+ const struct southbridge_intel_i82801jx_config *config;
+
+ /* Configure serial IRQs.*/
+ pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0);
+ /*
+ * Enable some common LPC IO ranges:
+ * - 0x2e/0x2f, 0x4e/0x4f often SuperIO
+ * - 0x60/0x64, 0x62/0x66 often KBC/EC
+ * - 0x3f0-0x3f5/0x3f7 FDD
+ * - 0x378-0x37f and 0x778-0x77f LPT
+ * - 0x2f8-0x2ff COMB
+ * - 0x3f8-0x3ff COMA
+ * - 0x208-0x20f GAMEH
+ * - 0x200-0x207 GAMEL
+ */
+ pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010);
+ pci_write_config16(d31f0, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
+ | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
+ | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+
+
+ /* Set up generic decode ranges */
+ if (!dev || !dev->chip_info)
+ return;
+ config = dev->chip_info;
+
+ pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec);
+ pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec);
+ pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec);
+ pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec);
+}
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 7b882181ff..e302c8986a 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -234,6 +234,7 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
const u8 *buf);
#endif
+void i82801jx_lpc_setup(void);
#endif