diff options
Diffstat (limited to 'src/southbridge/intel/i82801jx')
| -rw-r--r-- | src/southbridge/intel/i82801jx/acpi/ich10.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/early_init.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index d6136af14f..53ead1c967 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -112,7 +112,7 @@ Scope(\) // ICH10 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 771460955c..327c8fc0a5 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -50,7 +50,7 @@ void i82801jx_setup_bars(void) const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); /* Set up RCBA. */ - pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); /* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); |