7 files changed, 22 insertions, 17 deletions
diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c
index 3d9df6dd16..bca109a354 100644
--- a/src/southbridge/intel/i82801ix/dmi_setup.c
+++ b/src/southbridge/intel/i82801ix/dmi_setup.c
@@ -87,7 +87,7 @@ void i82801ix_dmi_setup(void)
 	RCBA8(RCBA_ULD + 3) = 1;
 	RCBA8(RCBA_ULD + 2) = 1;
 	/* Set target rcrb base address, i.e. DMIBAR. */
-	RCBA32(RCBA_ULBA) = DEFAULT_DMIBAR;
+	RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR;
 
 	/* Enable ASPM. */
 	if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) {
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index bd6548c6ba..1e3b517b1a 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -26,7 +26,7 @@ void i82801ix_early_init(void)
 	const device_t d31f0 = PCI_DEV(0, 0x1f, 0);
 
 	/* Set up RCBA. */
-	pci_write_config32(d31f0, D31F0_RCBA, DEFAULT_RCBA | 1);
+	pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1);
 
 	/* Set up PMBASE. */
 	pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);
diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c
index dd817b9b08..69c558dd06 100644
--- a/src/southbridge/intel/i82801ix/hdaudio.c
+++ b/src/southbridge/intel/i82801ix/hdaudio.c
@@ -35,7 +35,7 @@
 
 typedef struct southbridge_intel_i82801ix_config config_t;
 
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
 {
 	u32 reg32;
 	int count;
@@ -64,7 +64,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
 	return 0;
 }
 
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
 {
 	u32 reg32;
 
@@ -115,7 +115,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
  *  no response would imply that the codec is non-operative
  */
 
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u8 *base)
 {
 	/* Use a 50 usec timeout - the Linux kernel uses the
 	 * same duration */
@@ -123,7 +123,7 @@ static int wait_for_ready(u32 base)
 	int timeout = 50;
 
 	while(timeout--) {
-		u32 reg32 = read32(base +  HDA_ICII_REG);
+		u32 reg32 = read32(base + HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
 		udelay(1);
@@ -138,7 +138,7 @@ static int wait_for_ready(u32 base)
  *  is non-operative
  */
 
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u8 *base)
 {
 	u32 reg32;
 
@@ -162,7 +162,7 @@ static int wait_for_valid(u32 base)
 	return -1;
 }
 
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u8 *base, int addr)
 {
 	u32 reg32;
 	const u32 *verb;
@@ -206,7 +206,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
 	printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
 }
 
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
 {
 	int i;
 	for (i = 2; i >= 0; i--) {
@@ -227,7 +227,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
 
 static void azalia_init(struct device *dev)
 {
-	u32 base;
+	u8 *base;
 	struct resource *res;
 	u32 codec_mask;
 	u8 reg8;
@@ -281,7 +281,7 @@ static void azalia_init(struct device *dev)
 
 	// NOTE this will break as soon as the Azalia get's a bar above
 	// 4G. Is there anything we can do about it?
-	base = (u32)res->base;
+	base = res2mmio(res, 0, 0);
 	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
 	codec_mask = codec_detect(base);
 
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index d8dc077673..10b27179ca 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -27,8 +27,13 @@
 #endif
 #endif
 
-#define DEFAULT_TBAR		0xfed1b000
+#define DEFAULT_TBAR		((u8 *)0xfed1b000)
+#ifndef __ACPI__
+#define DEFAULT_RCBA		((u8 *)0xfed1c000)
+#else
 #define DEFAULT_RCBA		0xfed1c000
+#endif
+
 #ifdef CONFIG_BOARD_EMULATION_QEMU_X86_Q35
 /*
  * Qemu has the fw_cfg interface at 0x510.  Move the pmbase to a
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 6038eff114..0ba33d6759 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -62,7 +62,7 @@ static void i82801ix_enable_apic(struct device *dev)
 	*ioapic_index	= 0x01;
 	*ioapic_data	= reg32;
 
-	setup_ioapic(IO_APIC_ADDR, 2); /* ICH7 code uses id 2. */
+	setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */
 }
 
 static void i82801ix_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index 10c8a2bd15..f65eba26b4 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -36,8 +36,8 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
 	u32 reg32;
 
 	/* Initialize AHCI memory-mapped space */
-	const u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-	printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+	u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+	printk(BIOS_DEBUG, "ABAR: %p\n", abar);
 
 	/* Set AHCI access mode.
 	   No other ABAR registers should be accessed before this. */
@@ -67,7 +67,7 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
 	for (i = 0; i < 6; ++i) {
 		if (((i == 2) || (i == 3)) && is_mobile)
 			continue;
-		const u32 addr = abar + 0x118 + (i * 0x80);
+		u8 *addr = abar + 0x118 + (i * 0x80);
 		write32(addr, read32(addr));
 	}
 }
diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c
index 3245a27962..84afe93b54 100644
--- a/src/southbridge/intel/i82801ix/thermal.c
+++ b/src/southbridge/intel/i82801ix/thermal.c
@@ -34,7 +34,7 @@ static void thermal_init(struct device *dev)
 	u8 reg8;
 	u32 reg32;
 
-	pci_write_config32(dev, 0x10, DEFAULT_TBAR);
+	pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR);
 	reg32 = pci_read_config32(dev, 0x04);
 	pci_write_config32(dev, 0x04, reg32 | (1 << 1));