diff options
Diffstat (limited to 'src/southbridge/intel/i82801ix')
| -rw-r--r-- | src/southbridge/intel/i82801ix/early_init.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/i82801ix.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/smihandler.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 1d6c649369..3d94b566b1 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -42,7 +42,7 @@ void i82801ix_early_init(void) /* Enable upper 128bytes of CMOS. */ RCBA32(0x3400) = (1 << 2); - /* Initialize power manangement initialization + /* Initialize power management initialization register early as it affects reboot behavior. */ /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6 and 0xe (required if ME is disabled but present), bit 31 locks it. diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index d5bcbc2a42..afe4aa7064 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -193,7 +193,7 @@ #define RCBA_FD 0x3418 /* Function Disable, see below. */ #define RCBA_CG 0x341c #define RCBA_FDSW 0x3420 -#define RCBA_MAP 0x35f0 /* UHCI cotroller #6 remapping */ +#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */ #define BUC_LAND (1 << 5) /* LAN */ #define FD_SAD2 (1 << 25) /* SATA #2 */ diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 7beb999900..9e04328989 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -511,7 +511,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav if (southbridge_smi[i]) southbridge_smi[i](node, state_save); else { - printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " + printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no " "handler available.\n", i); dump = 1; } |