aboutsummaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801ix
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/i82801ix')
-rw-r--r--src/southbridge/intel/i82801ix/acpi/globalnvs.asl2
-rw-r--r--src/southbridge/intel/i82801ix/include/soc/nvs.h2
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c8
3 files changed, 2 insertions, 10 deletions
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
index 24efba67f8..d2af885b0e 100644
--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
@@ -46,7 +46,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Processor Identification */
Offset (0x28),
, 8, // 0x28 - Enabled by coreboot
- MPEN, 8, // 0x29 - Multi Processor Enable
+ , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state
diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h
index 4fa56763bc..2d4980bec3 100644
--- a/src/southbridge/intel/i82801ix/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h
@@ -41,7 +41,7 @@ struct __packed global_nvs {
u8 rsvd3[3];
/* Processor Identification */
u8 unused_was_apic; /* 0x28 - APIC enabled */
- u8 mpen; /* 0x29 - MP capable/enabled */
+ u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 5400237fa8..b84b458027 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -12,7 +12,6 @@
#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
-#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <acpi/acpigen.h>
#include <string.h>
@@ -21,7 +20,6 @@
#include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
-#include <soc/nvs.h>
#define NMI_OFF 0
@@ -452,12 +450,6 @@ static void i82801ix_lpc_read_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-void soc_fill_gnvs(struct global_nvs *gnvs)
-{
- /* MPEN, Enable Multi Processing. */
- gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0;
-}
-
static const char *lpc_acpi_name(const struct device *dev)
{
return "LPCB";