diff options
Diffstat (limited to 'src/southbridge/intel/i82801gx')
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/globalnvs.asl | 12 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/ich7.asl | 74 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl | 41 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/ich7_pci.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl | 12 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/sleepstates.asl | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/chip.h | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 99 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_azalia.c | 113 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_ide.c | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_lpc.c | 55 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_nvs.h | 15 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_sata.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_smi.c | 54 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_smihandler.c | 99 |
16 files changed, 307 insertions, 309 deletions
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 5ac1c83cd6..0384376417 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -81,7 +81,16 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PPCM, 8, // 0x2c - Max. PPC state /* Super I/O & CMOS config */ Offset (0x32), - NATP, 8, // 0x32 - ... + NATP, 8, // 0x32 - + CMAP, 8, // 0x33 - + CMBP, 8, // 0x34 - + LPTP, 8, // 0x35 - LPT Port + FDCP, 8, // 0x36 - Floppy Disk Controller + RFDV, 8, // 0x37 - + HOTK, 8, // 0x38 - + RTCF, 8, // 0x39 - + UTIL, 8, // 0x3a - + ACIN, 8, // 0x3b - /* Integrated Graphics Device */ Offset (0x3c), IGDS, 8, // 0x3c - IGD state (primary = 1) @@ -158,4 +167,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Mainboard Specific (TODO move elsewhere) */ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status + BTEN, 8, // 0xf1 - Bluetooth Enable } diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 3f845c483b..a37208c021 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -19,8 +19,7 @@ * MA 02110-1301 USA */ -/* Intel i82801G support - */ +/* Intel 82801Gx support */ Scope(\) { @@ -34,10 +33,7 @@ Scope(\) } // ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l) - // this doesn't work as ACPI initializes regions and packages first, devices second. - // use dynamic operation region? if so, how? XXX - //OperationRegion(PMIO, SystemIO, And(\_SB_.PCI0.LPCB.PMBS, 0xfffc), 0x80) - OperationRegion(PMIO, SystemIO, 0x500, 0x80) + OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) Field(PMIO, ByteAcc, NoLock, Preserve) { Offset(0x42), // General Purpose Control @@ -49,7 +45,7 @@ Scope(\) } // ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l) - OperationRegion(GPIO, SystemIO, 0x1180, 0x3c) + OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) Field(GPIO, ByteAcc, NoLock, Preserve) { Offset(0x00), // GPIO Use Select @@ -63,12 +59,32 @@ Scope(\) GIO2, 8, GIO3, 8, Offset(0x0c), // GPIO Level - GL00, 8, - GL01, 8, - , 3, - GP27, 1, // SATA_PWR_EN #0 - GP28, 1, // SATA_PWR_EN #1 - , 3, + GL00, 6, + GP07, 1, // GDET + GP08, 1, + GP09, 1, + GP10, 1, // HPMU + GP11, 1, // GPSE + GP12, 1, + GP13, 1, // WLED + GP14, 1, // BLED + GP15, 1, // GLED + GP16, 1, // GDIS + GP17, 1, + GP18, 1, + GP19, 1, // SPCI + GP20, 1, // TSDT + GP21, 1, // SCPU + GP22, 1, + GP23, 1, + GP24, 1, // LANP + GP25, 1, // DKLR + GP26, 1, // WLAN + GP27, 1, // SATA_PWR_EN #0 / SPOF + GP28, 1, // SATA_PWR_EN #1 / SPMU + GP29, 1, + GP30, 1, + GP31, 1, Offset(0x18), // GPIO Blink GB00, 8, GB01, 8, @@ -90,10 +106,14 @@ Scope(\) GIO6, 8, GIO7, 8, Offset(0x38), // GPIO Level 2 - , 5, - GP37, 1, // PATA_PWR_EN - GP38, 1, // Battery / Power (?) - GP39, 1, // ?? + GP32, 1, + GP33, 1, // CREN + GP34, 1, // CRRS + GP35, 1, + GP36, 1, // STAD + GP37, 1, // PATA_PWR_EN / HDDE + GP38, 1, // Battery / Power (?) / MB00 + GP39, 1, // ?? / MB01 GL05, 8, GL06, 8, GL07, 8 @@ -101,7 +121,7 @@ Scope(\) // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, 0xfed1c000, 0x4000) + OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone @@ -139,30 +159,30 @@ Scope(\) } // 0:1b.0 High Definition Audio (Azalia) -Include ("../../../southbridge/intel/i82801gx/acpi/ich7_audio.asl") +#include "../../../southbridge/intel/i82801gx/acpi/ich7_audio.asl" // PCI Express Ports -Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pcie.asl") +#include "../../../southbridge/intel/i82801gx/acpi/ich7_pcie.asl" // USB -Include ("../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl") +#include "../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl" // PCI Bridge -Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl") +#include "../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl" // AC97 Audio and Modem -Include ("../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl") +#include "../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl" // LPC Bridge -Include ("../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl") +#include "../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl" // PATA -Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pata.asl") +#include "../../../southbridge/intel/i82801gx/acpi/ich7_pata.asl" // SATA -Include ("../../../southbridge/intel/i82801gx/acpi/ich7_sata.asl") +#include "../../../southbridge/intel/i82801gx/acpi/ich7_sata.asl" // SMBus -Include ("../../../southbridge/intel/i82801gx/acpi/ich7_smbus.asl") +#include "../../../southbridge/intel/i82801gx/acpi/ich7_smbus.asl" diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl b/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl index fdf05b2e2f..a18673c679 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl @@ -51,9 +51,9 @@ Device (LPCB) RCBA, 18, } - Include ("../../../southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl") + #include "../../../southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl" - Include ("acpi/ec.asl") + #include "acpi/ec.asl" Device (DMAC) // DMA Controller { @@ -174,11 +174,9 @@ Device (LPCB) IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - // IO (Decode16, 0x680, 0x680, 0x1, 0x70) // IO ??? IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap - IO (Decode16, 0x0500, 0x0500, 0x1, 0x80) // ICH7-M ACPI - IO (Decode16, 0x0480, 0x0480, 0x1, 0x40) // ICH7-M GPIO - // IO (Decode16, 0x1640, 0x1640, 0x1, 0x10) // IO ??? + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI + IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO }) } @@ -188,7 +186,8 @@ Device (LPCB) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) - IRQNoFlags() { 8 } +// Disable as Windows doesn't like it, and systems don't seem to use it. +// IRQNoFlags() { 8 } }) } @@ -203,7 +202,31 @@ Device (LPCB) }) } - Include ("acpi/superio.asl") + #include "acpi/superio.asl" + +#ifdef ENABLE_TPM + Device (TPM) // Trusted Platform Module + { + Name(_HID, EISAID("IFX0102")) + Name(_CID, 0x310cd041) + Name(_UID, 1) + + Method(_STA, 0) + { + If (TPMP) { + Return (0xf) + } + Return (0x0) + } + + Name(_CRS, ResourceTemplate() { + IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) + IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) + Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) + IRQ (Edge, Activehigh, Exclusive) { 6 } + }) + } +#endif Device (PS2K) // Keyboard { @@ -237,6 +260,7 @@ Device (LPCB) } } +#ifdef ENABLE_FDC Device (FDC0) // Floppy controller { Name (_HID, EisaId ("PNP0700")) @@ -262,4 +286,5 @@ Device (LPCB) }) } +#endif } diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl b/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl index 9bcf58e413..d253d51a78 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl @@ -70,7 +70,7 @@ Device (PCIB) Method (_PRT) { - Include ("acpi/ich7_pci_irqs.asl") + #include "acpi/ich7_pci_irqs.asl" } } diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl b/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl index 0822e8ee02..a76c7fbe4d 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl @@ -26,7 +26,7 @@ Device (RP01) { NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //Include ("pcie_port.asl") + //#include "pcie_port.asl" Method(_PRT) { If (PICM) { @@ -52,7 +52,7 @@ Device (RP01) Device (RP02) { NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //Include ("pcie_port.asl") + //#include "pcie_port.asl" Method(_PRT) { If (PICM) { @@ -79,7 +79,7 @@ Device (RP02) Device (RP03) { NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //Include ("pcie_port.asl") + //#include "pcie_port.asl" Method(_PRT) { If (PICM) { @@ -106,7 +106,7 @@ Device (RP03) Device (RP04) { NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //Include ("pcie_port.asl") + //#include "pcie_port.asl" Method(_PRT) { If (PICM) { @@ -133,7 +133,7 @@ Device (RP04) Device (RP05) { NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //Include ("pcie_port.asl") + //#include "pcie_port.asl" Method(_PRT) { If (PICM) { @@ -160,7 +160,7 @@ Device (RP05) Device (RP06) { NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //Include ("pcie_port.asl") + //#include "pcie_port.asl" Method(_PRT) { If (PICM) { diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl b/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl index b7d807ee44..b6d2d6a2ab 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl @@ -33,7 +33,6 @@ Device (SBUS) I2CE, 1 } - /* OperationRegion (SMBI, SystemIO, 0x400, 0x20) Field (SMBI, ByteAcc, NoLock, Preserve) { @@ -59,6 +58,7 @@ Device (SBUS) NDLH, 8, // Notify Data High Byte } +#ifdef ENABLE_SMBUS_METHODS // Kill all SMBus communication Method (KILL, 0, Serialized) { @@ -237,10 +237,6 @@ Device (SBUS) Return (0xffff) } - */ - - // Todo: Does anyone ever use these? - // Missing: Read / Write Word - // Missing: Read / Write Block +#endif } diff --git a/src/southbridge/intel/i82801gx/acpi/sleepstates.asl b/src/southbridge/intel/i82801gx/acpi/sleepstates.asl index 61595854b2..863eee72dd 100644 --- a/src/southbridge/intel/i82801gx/acpi/sleepstates.asl +++ b/src/southbridge/intel/i82801gx/acpi/sleepstates.asl @@ -19,9 +19,9 @@ * MA 02110-1301 USA */ -Name(\_S0, Package(4){0x0,0x0,0,0}) -Name(\_S1, Package(4){0x1,0x0,0,0}) -Name(\_S3, Package(4){0x5,0x0,0,0}) -Name(\_S4, Package(4){0x6,0x0,0,0}) -Name(\_S5, Package(4){0x7,0x0,0,0}) +Name(\_S0, Package(){0x0,0x0,0,0}) +Name(\_S1, Package(){0x1,0x0,0,0}) +Name(\_S3, Package(){0x5,0x0,0,0}) +Name(\_S4, Package(){0x6,0x0,0,0}) +Name(\_S5, Package(){0x7,0x0,0,0}) diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 7fca7ca9f3..7b16e8b3dc 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -61,14 +61,14 @@ struct southbridge_intel_i82801gx_config { uint8_t gpi14_routing; uint8_t gpi15_routing; + uint32_t gpe0_en; + uint16_t alt_gp_smi_en; + /* IDE configuration */ uint32_t ide_legacy_combined; uint32_t ide_enable_primary; uint32_t ide_enable_secondary; uint32_t sata_ahci; - - /* Azalia Configuration */ - uint32_t hda_viddid; }; extern struct chip_operations southbridge_intel_i82801gx_ops; diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 98c62ce091..9b54fc6008 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -20,6 +20,23 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H +/* + * It does not matter where we put the SMBus I/O base, as long as we + * keep it consistent and don't interfere with other devices. Stage2 + * will relocate this anyways. + * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE + * again. But handling static BARs is a generic problem that should be + * solved in the device allocator. + */ +#define SMBUS_IO_BASE 0x0400 +/* TODO Make sure these don't get changed by stage2 */ +#define DEFAULT_GPIOBASE 0x0480 +#define DEFAULT_PMBASE 0x0500 +#define HPET_ADDR 0xfed00000 +#define DEFAULT_RCBA 0xfed1c000 + +#ifndef __ACPI__ +#define DEBUG_PERIODIC_SMIS 0 /* __ROMCC__ is set by auto.c to make sure * none of the stage2 data structures are included. @@ -91,11 +108,18 @@ extern void i82801gx_enable(device_t dev); #define IDE_SDMA_TIM 0x4a #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_NORMAL (0 << 16) -#define SIG_MODE_TRISTATE (1 << 16) -#define SIG_MODE_DRIVELOW (2 << 16) +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) #define FAST_PCB1 (1 << 13) #define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) #define PCB1 (1 << 1) #define PCB0 (1 << 0) @@ -108,16 +132,7 @@ extern void i82801gx_enable(device_t dev); #define SMB_SMI_EN (1 << 1) #define HST_EN (1 << 0) -/* SMBus I/O bits. - * It does not matter where we put the SMBus I/O base, as long as we - * keep it consistent and don't interfere with other devices. Stage2 - * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE - * again. But handling static BARs is a generic problem that should be - * solved in the device allocator. - */ -#define SMBUS_IO_BASE 0x0400 - +/* SMBus I/O bits. */ #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 #define SMBHSTCMD 0x3 @@ -132,21 +147,15 @@ extern void i82801gx_enable(device_t dev); #define SMBUS_TIMEOUT (10 * 1000 * 100) -/* HPET, if present */ -#define HPET_ADDR 0xfed0000 /* Southbridge IO BARs */ -/* TODO Make sure these don't get changed by stage2 */ #define GPIOBASE 0x48 -#define DEFAULT_GPIOBASE 0x480 #define PMBASE 0x40 -#define DEFAULT_PMBASE 0x500 /* Root Complex Register Block */ #define RCBA 0xf0 -#define DEFAULT_RCBA 0xfed1c000 #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) @@ -255,4 +264,56 @@ extern void i82801gx_enable(device_t dev); #define FD_SATA (1 << 2) #define FD_PATA (1 << 1) +/* ICH7 GPIOBASE */ +#define GPIO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GPIO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 + +/* ICH7 PMBASE */ +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define PROC_CNT 0x10 +#define LV2 0x14 +#define LV3 0x15 +#define LV4 0x16 +#define PM2_CNT 0x20 // mobile only +#define GPE0_STS 0x28 +#define GPE0_EN 0x2c +#define PME_B0_EN (1 << 13) +#define SMI_EN 0x30 +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define SMI_STS 0x34 +#define ALT_GP_SMI_EN 0x38 +#define ALT_GP_SMI_STS 0x3a +#define GPE_CNTL 0x42 +#define DEVACT_STS 0x44 +#define SS_CNT 0x50 +#define C3_RES 0x54 + +#endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/i82801gx_azalia.c index 1435866100..fd71813f5a 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c +++ b/src/southbridge/intel/i82801gx/i82801gx_azalia.c @@ -90,93 +90,25 @@ no_codec: return 0; } -static u32 cim_verb_data[] = { - 0x00172000, - 0x00172100, - 0x001722EC, - 0x00172310, - - /* Pin Complex (NID 0x12) */ - 0x01271CF0, - 0x01271D11, - 0x01271E11, - 0x01271F41, - /* Pin Complex (NID 0x14) */ - 0x01471C10, - 0x01471D01, - 0x01471E13, - 0x01471F99, - /* Pin Complex (NID 0x15) */ - 0x01571C20, - 0x01571D40, - 0x01571E21, - 0x01571F01, - /* Pin Complex (NID 0x16) */ - 0x01671CF0, - 0x01671D11, - 0x01671E11, - 0x01671F41, - /* Pin Complex (NID 0x18) */ - 0x01871C30, - 0x01871D98, - 0x01871EA1, - 0x01871F01, - /* Pin Complex (NID 0x19) */ - 0x01971C31, - 0x01971D09, - 0x01971EA3, - 0x01971F99, - /* Pin Complex (NID 0x1A) */ - 0x01A71C3F, - 0x01A71D98, - 0x01A71EA1, - 0x01A71F02, - /* Pin Complex (NID 0x1B) */ - 0x01B71C1F, - 0x01B71D40, - 0x01B71E21, - 0x01B71F02, - /* Pin Complex (NID 0x1C) */ - 0x01C71CF0, - 0x01C71D11, - 0x01C71E11, - 0x01C71F41, - /* Pin Complex (NID 0x1D) */ - 0x01D71CF0, - 0x01D71D11, - 0x01D71E11, - 0x01D71F41, - /* Pin Complex (NID 0x1E) */ - 0x01E71CF0, - 0x01E71D11, - 0x01E71E11, - 0x01E71F41, - /* Pin Complex (NID 0x1F) */ - 0x01F71CF0, - 0x01F71D11, - 0x01F71E11, - 0x01F71F41, -}; +u32 * cim_verb_data = NULL; +u32 cim_verb_data_size = 0; -static unsigned find_verb(struct device *dev, u32 viddid, u32 ** verb) +static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb) { - config_t *config = dev->chip_info; - - if (config == NULL) { - printk_err("\ni82801gx_azalia: Not mentioned in mainboard's Config.lb!\n"); - return 0; + int idx=0; + + while (idx < (cim_verb_data_size / sizeof(u32))) { + u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + if (cim_verb_data[idx] != viddid) { + idx += verb_size + 3; // skip verb + header + continue; + } + *verb = &cim_verb_data[idx+3]; + return verb_size; } - printk_debug("Azalia: dev=%s\n", dev_path(dev)); - printk_debug("Azalia: Default viddid=%x\n", (u32)config->hda_viddid); - printk_debug("Azalia: Reading viddid=%x\n", viddid); - - if (viddid != config->hda_viddid) - return 0; - - *verb = (u32 *) cim_verb_data; - - return sizeof(cim_verb_data) / sizeof(u32); + /* Not all codecs need to load another verb */ + return 0; } /** @@ -209,19 +141,26 @@ static int wait_for_ready(u8 *base) static int wait_for_valid(u8 *base) { + u32 reg32; + + /* Send the verb to the codec */ + reg32 = readl(base + 0x68); + reg32 |= (1 << 0) | (1 << 1); + writel(reg32, base + 0x68); + /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ int timeout = 50; while(timeout--) { - u32 reg32 = readl(base + HDA_ICII_REG); + reg32 = readl(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } - return 1; + return -1; } static void codec_init(struct device *dev, u8 * base, int addr) @@ -231,6 +170,8 @@ static void codec_init(struct device *dev, u8 * base, int addr) u32 verb_size; int i; + printk_debug("Azalia: Initializing codec #%d\n", addr); + /* 1 */ if (wait_for_ready(base) == -1) return; @@ -251,8 +192,8 @@ static void codec_init(struct device *dev, u8 * base, int addr) printk_debug("Azalia: No verb!\n"); return; } - printk_debug("Azalia: verb_size: %d\n", verb_size); + /* 3 */ for (i = 0; i < verb_size; i++) { if (wait_for_ready(base) == -1) diff --git a/src/southbridge/intel/i82801gx/i82801gx_ide.c b/src/southbridge/intel/i82801gx/i82801gx_ide.c index c29e678a69..28a1c055ea 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_ide.c +++ b/src/southbridge/intel/i82801gx/i82801gx_ide.c @@ -38,7 +38,7 @@ static void ide_init(struct device *dev) printk_debug("i82801gx_ide: initializing... "); if (config == NULL) { printk_err("\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n"); - // Trying to set somewhat save defaults instead of bailing out. + // Trying to set somewhat safe defaults instead of bailing out. enable_primary = enable_secondary = 1; } else { enable_primary = config->ide_enable_primary; @@ -80,10 +80,12 @@ static void ide_init(struct device *dev) pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); /* Set IDE I/O Configuration */ + reg32 = 0; + /* FIXME: only set FAST_* for ata/100, only ?CBx for ata/66 */ + if (enable_primary) + reg32 |= SIG_MODE_PRI_NORMAL | FAST_PCB0 | PCB0 | FAST_PCB1 | PCB1; if (enable_secondary) - reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - else - reg32 = SIG_MODE_NORMAL | FAST_PCB1 | PCB1; + reg32 |= SIG_MODE_SEC_NORMAL | FAST_SCB0 | SCB0 | FAST_SCB1 | SCB1; pci_write_config32(dev, IDE_CONFIG, reg32); /* Set Interrupt Line */ diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c index bed5dce2c2..a99e50e61e 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c +++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c @@ -36,36 +36,6 @@ typedef struct southbridge_intel_i82801gx_config config_t; -/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -#define PIRQA 0x03 -#define PIRQB 0x05 -#define PIRQC 0x06 -#define PIRQD 0x07 -#define PIRQE 0x09 -#define PIRQF 0x0A -#define PIRQG 0x0B -#define PIRQH 0x0C - static void i82801gx_enable_apic(struct device *dev) { int i; @@ -206,6 +176,8 @@ static void i82801gx_power_options(device_t dev) u16 reg16, pmbase; u32 reg32; char *state; + /* Get the chip configuration */ + config_t *config = dev->chip_info; int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; int nmi_option; @@ -213,8 +185,12 @@ static void i82801gx_power_options(device_t dev) /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off + * + * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - get_option(&pwr_on, "power_on_after_fail"); + if (get_option(&pwr_on, "power_on_after_fail") < 0) + pwr_on = MAINBOARD_POWER_ON; + reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; switch (pwr_on) { @@ -265,19 +241,31 @@ static void i82801gx_power_options(device_t dev) reg16 &= ~((3 << 0) | (1 << 10)); reg16 |= (1 << 3) | (1 << 5); reg16 |= (1 << 2); // CLKRUN_EN +#if DEBUG_PERIODIC_SMIS + /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using + * periodic SMIs. + */ + reg16 |= (3 << 0); // Periodic SMI every 8s +#endif pci_write_config16(dev, GEN_PMCON_1, reg16); // Set the board's GPI routing. i82801gx_gpi_routing(dev); - /* Set up power management block and determine sleep mode */ pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + + outl(config->gpe0_en, pmbase + GPE0_EN); + outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); + + /* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); // PM1_CNT +#if 0 #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = (((reg32 >> 10) & 7) == 5) ? 3 : 0; printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n", reg32, acpi_slp_type); #endif +#endif reg32 |= (1 << 1); // enable C3->C0 transition on bus master reg32 |= 1; // SCI_EN outl(reg32, pmbase + 0x04); @@ -448,6 +436,9 @@ static void lpc_init(struct device *dev) setup_i8259(); + /* The OS should do this? */ + // i8259_configure_irq_trigger(9, 1); + #if CONFIG_HAVE_SMI_HANDLER i82801gx_lock_smm(dev); #endif diff --git a/src/southbridge/intel/i82801gx/i82801gx_nvs.h b/src/southbridge/intel/i82801gx/i82801gx_nvs.h index 7f245dd11a..dffee3f045 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_nvs.h +++ b/src/southbridge/intel/i82801gx/i82801gx_nvs.h @@ -62,12 +62,12 @@ typedef struct { u8 rsvd4[5]; /* Super I/O & CMOS config */ u8 natp; /* 0x32 - SIO type */ - u8 cmap; - u8 cmbp; - u8 lptp; - u8 fdcp; - u8 rfdv; - u8 hotk; + u8 cmap; /* 0x33 - */ + u8 cmbp; /* 0x34 - */ + u8 lptp; /* 0x35 - LPT port */ + u8 fdcp; /* 0x36 - Floppy Disk Controller */ + u8 rfdv; /* 0x37 - */ + u8 hotk; /* 0x38 - Hot Key */ u8 rtcf; u8 util; u8 acin; @@ -134,6 +134,7 @@ typedef struct { u8 rsvd12[8]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ - u8 rsvd13[15]; + u8 bten; + u8 rsvd13[14]; } __attribute__((packed)) global_nvs_t; diff --git a/src/southbridge/intel/i82801gx/i82801gx_sata.c b/src/southbridge/intel/i82801gx/i82801gx_sata.c index ddfe08d25a..ec477e1696 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_sata.c +++ b/src/southbridge/intel/i82801gx/i82801gx_sata.c @@ -68,7 +68,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* Combine IDE - SATA configuration */ @@ -100,7 +100,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* Set Sata Controller Mode. */ @@ -146,7 +146,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* Port 0 & 1 enable XXX */ diff --git a/src/southbridge/intel/i82801gx/i82801gx_smi.c b/src/southbridge/intel/i82801gx/i82801gx_smi.c index c8b5a16ccb..7fb4abfdaa 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_smi.c +++ b/src/southbridge/intel/i82801gx/i82801gx_smi.c @@ -40,41 +40,6 @@ extern unsigned int smm_len; #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -/* ICH7 */ -#define PM1_STS 0x00 -#define PM1_EN 0x02 -#define PM1_CNT 0x04 -#define PM1_TMR 0x08 -#define PROC_CNT 0x10 -#define LV2 0x14 -#define LV3 0x15 -#define LV4 0x16 -#define PM2_CNT 0x20 // mobile only -#define GPE0_STS 0x28 -#define GPE0_EN 0x2c -#define SMI_EN 0x30 -#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? -#define SMI_STS 0x34 -#define ALT_GP_SMI_EN 0x38 -#define ALT_GP_SMI_STS 0x3a -#define GPE_CNTL 0x42 -#define DEVACT_STS 0x44 -#define SS_CNT 0x50 -#define C3_RES 0x54 - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ @@ -277,8 +242,23 @@ void smm_relocate(void) * No SMIs: * - on microcontroller writes (io 0x62/0x66) */ - outl(smi_en | (TCO_EN | APMC_EN | SLP_SMI_EN | BIOS_EN | - EOS | GBL_SMI_EN), pmbase + SMI_EN); + + smi_en = 0; /* reset SMI enables */ + smi_en |= TCO_EN; + smi_en |= APMC_EN; +#if DEBUG_PERIODIC_SMIS + /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using + * periodic SMIs. + */ + smi_en |= PERIODIC_EN; +#endif + smi_en |= SLP_SMI_EN; + smi_en |= BIOS_EN; + + /* The following need to be on for SMIs to happen */ + smi_en |= EOS | GBL_SMI_EN; + + outl(smi_en, pmbase + SMI_EN); /** * There are several methods of raising a controlled SMI# via diff --git a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c index 56ce0fe0eb..8cf39e8ded 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c +++ b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c @@ -46,53 +46,13 @@ #define G_SMRANE (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -/* ICH7 */ -#define PM1_STS 0x00 -#define PM1_EN 0x02 -#define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define PROC_CNT 0x10 -#define LV2 0x14 -#define LV3 0x15 -#define LV4 0x16 -#define PM2_CNT 0x20 // mobile only -#define GPE0_STS 0x28 -#define GPE0_EN 0x2c -#define PME_B0_EN (1 << 13) -#define SMI_EN 0x30 -#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? -#define SMI_STS 0x34 -#define ALT_GP_SMI_EN 0x38 -#define ALT_GP_SMI_STS 0x3a -#define GPE_CNTL 0x42 -#define DEVACT_STS 0x44 -#define SS_CNT 0x50 -#define C3_RES 0x54 - #include "i82801gx_nvs.h" /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; +u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. @@ -118,16 +78,16 @@ static u16 reset_pm1_status(void) static void dump_pm1_status(u16 pm1_sts) { - printk_debug("PM1_STS: "); - if (pm1_sts & (1 << 15)) printk_debug("WAK "); - if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR "); - if (pm1_sts & (1 << 10)) printk_debug("RTC "); - if (pm1_sts & (1 << 8)) printk_debug("PWRBTN "); - if (pm1_sts & (1 << 5)) printk_debug("GBL "); - if (pm1_sts & (1 << 4)) printk_debug("BM "); - if (pm1_sts & (1 << 0)) printk_debug("TMROF "); - printk_debug("\n"); + printk_spew("PM1_STS: "); + if (pm1_sts & (1 << 15)) printk_spew("WAK "); + if (pm1_sts & (1 << 14)) printk_spew("PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk_spew("PRBTNOR "); + if (pm1_sts & (1 << 10)) printk_spew("RTC "); + if (pm1_sts & (1 << 8)) printk_spew("PWRBTN "); + if (pm1_sts & (1 << 5)) printk_spew("GBL "); + if (pm1_sts & (1 << 4)) printk_spew("BM "); + if (pm1_sts & (1 << 0)) printk_spew("TMROF "); + printk_spew("\n"); } /** @@ -261,21 +221,16 @@ int southbridge_io_trap_handler(int smif) switch (smif) { case 0x32: printk_debug("OS Init\n"); + /* gnvs->smif: + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + */ gnvs->smif = 0; - break; - default: - /* Not handled */ - return 0; + return 1; /* IO trap handled */ } - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - //gnvs->smif = 0; - return 1; /* IO trap handled */ + /* Not handled */ + return 0; } /** @@ -400,9 +355,14 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state printk_debug("SMI#: ACPI enabled.\n"); break; case GNVS_UPDATE: + if (smm_initialized) { + printk_debug("SMI#: SMM structures already initialized!\n"); + return; + } gnvs = *(global_nvs_t **)0x500; tcg = *(void **)0x504; smi1 = *(void **)0x508; + smm_initialized = 1; printk_debug("SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1); break; default: @@ -426,6 +386,17 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state dump_gpe0_status(gpe0_sts); } +static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) +{ + u16 reg16; + reg16 = inw(pmbase + ALT_GP_SMI_STS); + outl(reg16, pmbase + ALT_GP_SMI_STS); + + reg16 &= inw(pmbase + ALT_GP_SMI_EN); + if (reg16) + printk_debug("GPI (mask %04x)\n",reg16); +} + static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) { u32 reg32; @@ -559,7 +530,7 @@ smi_handler southbridge_smi[32] = { NULL, // [7] reserved southbridge_smi_pm1, // [8] PM1_STS southbridge_smi_gpe0, // [9] GPE0_STS - NULL, // [10] GPI_STS + southbridge_smi_gpi, // [10] GPI_STS southbridge_smi_mc, // [11] MCSMI_STS NULL, // [12] DEVMON_STS southbridge_smi_tco, // [13] TCO_STS |