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Diffstat (limited to 'src/southbridge/intel/i82801gx')
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801gx/early_smbus.c51
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h16
-rw-r--r--src/southbridge/intel/i82801gx/smbus.c148
-rw-r--r--src/southbridge/intel/i82801gx/smbus.h92
5 files changed, 4 insertions, 304 deletions
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index b2265c4902..68c236299e 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -24,6 +24,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
select HAVE_SMI_HANDLER
select COMMON_FADT
select SOUTHBRIDGE_INTEL_COMMON_GPIO
+ select SOUTHBRIDGE_INTEL_COMMON_SMBUS
if SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c
index b8852e91ab..5d204e9527 100644
--- a/src/southbridge/intel/i82801gx/early_smbus.c
+++ b/src/southbridge/intel/i82801gx/early_smbus.c
@@ -18,8 +18,8 @@
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
+#include <southbridge/intel/common/smbus.h>
#include "i82801gx.h"
-#include "smbus.h"
void enable_smbus(void)
{
@@ -57,52 +57,5 @@ int smbus_read_byte(unsigned int device, unsigned int address)
int i2c_block_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf)
{
- u8 status;
- int bytes_read = 0;
- if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0)
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-
- /* Setup transaction */
- /* Disable interrupts */
- outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
- /* Set the device I'm talking to */
- outb((device & 0x7f) << 1, SMBUS_IO_BASE + SMBXMITADD);
-
- /* SPD offset */
- outb(offset, SMBUS_IO_BASE + SMBHSTDAT1);
-
- /* Set up for a i2c block data read */
- outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xc3) | (0x6 << 2),
- (SMBUS_IO_BASE + SMBHSTCTL));
-
- /* Clear any lingering errors, so the transaction will run */
- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- /* Start the command */
- outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
- SMBUS_IO_BASE + SMBHSTCTL);
-
- while (!(inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1))
- ;
- /* Poll for transaction completion */
- do {
- status = inb(SMBUS_IO_BASE + SMBHSTSTAT);
- if (status & ((1 << 4) | /* FAILED */
- (1 << 3) | /* BUS ERR */
- (1 << 2))) /* DEV ERR */
- return SMBUS_ERROR;
-
- if (status & 0x80) { /* Byte done */
- *buf = inb(SMBUS_IO_BASE + SMBBLKDAT);
- buf++;
- bytes_read++;
- if (--bytes == 1) {
- /* indicate that next byte is the last one */
- outb(inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x20,
- SMBUS_IO_BASE + SMBHSTCTL);
- }
- outb(status, SMBUS_IO_BASE + SMBHSTSTAT);
- }
- } while (status & 0x01);
-
- return bytes_read;
+ return do_i2c_block_read(SMBUS_IO_BASE, device, offset, bytes, buf);
}
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 0dc4c0b9fd..d1c861ddeb 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -177,22 +177,6 @@ int southbridge_detect_s3_resume(void);
#define SMB_SMI_EN (1 << 1)
#define HST_EN (1 << 0)
-/* SMBus I/O bits. */
-#define SMBHSTSTAT 0x0
-#define SMBHSTCTL 0x2
-#define SMBHSTCMD 0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT 0x7
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
-
-#define SMBUS_TIMEOUT (10 * 1000 * 100)
-
-
/* Southbridge IO BARs */
#define GPIOBASE 0x48
diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c
index d028f73367..fdf76a03e5 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -22,8 +22,8 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
+#include <southbridge/intel/common/smbus.h>
#include "i82801gx.h"
-#include "smbus.h"
static int lsmbus_read_byte(device_t dev, u8 address)
{
@@ -38,49 +38,6 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
-static int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
- unsigned int address, unsigned int data)
-{
- unsigned char global_status_register;
-
- if (smbus_wait_until_ready(smbus_base) < 0)
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-
- /* Setup transaction */
- /* Disable interrupts */
- outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
- /* Set the device I'm talking too */
- outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
- /* Set the command/address... */
- outb(address & 0xff, smbus_base + SMBHSTCMD);
- /* Set up for a byte data read */
- outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
- (smbus_base + SMBHSTCTL));
- /* Clear any lingering errors, so the transaction will run */
- outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
-
- /* Clear the data byte... */
- outb(data, smbus_base + SMBHSTDAT0);
-
- /* Start the command */
- outb((inb(smbus_base + SMBHSTCTL) | 0x40),
- smbus_base + SMBHSTCTL);
-
- /* Poll for transaction completion */
- if (smbus_wait_until_done(smbus_base) < 0)
- return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
-
- global_status_register = inb(smbus_base + SMBHSTSTAT);
-
- /* Ignore the "In Use" status... */
- global_status_register &= ~(3 << 5);
-
- /* Read results of transaction */
- if (global_status_register != (1 << 1))
- return SMBUS_ERROR;
- return 0;
-}
-
static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
{
u16 device;
@@ -93,58 +50,6 @@ static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
return do_smbus_write_byte(res->base, device, address, data);
}
-static int do_smbus_block_write(unsigned int smbus_base, unsigned int device,
- unsigned int cmd, unsigned int bytes, const u8 *buf)
-{
- u8 status;
-
- if (smbus_wait_until_ready(smbus_base) < 0)
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-
- /* Setup transaction */
- /* Disable interrupts */
- outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
- /* Set the device I'm talking too */
- outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
- /* Set the command/address... */
- outb(cmd & 0xff, smbus_base + SMBHSTCMD);
- /* Set up for a block data write */
- outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2),
- (smbus_base + SMBHSTCTL));
- /* Clear any lingering errors, so the transaction will run */
- outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
-
- /* set number of bytes to transfer */
- outb(bytes, smbus_base + SMBHSTDAT0);
-
- outb(*buf++, smbus_base + SMBBLKDAT);
- bytes--;
-
- /* Start the command */
- outb((inb(smbus_base + SMBHSTCTL) | 0x40),
- smbus_base + SMBHSTCTL);
-
- while (!(inb(smbus_base + SMBHSTSTAT) & 1))
- ;
- /* Poll for transaction completion */
- do {
- status = inb(smbus_base + SMBHSTSTAT);
- if (status & ((1 << 4) | /* FAILED */
- (1 << 3) | /* BUS ERR */
- (1 << 2))) /* DEV ERR */
- return SMBUS_ERROR;
-
- if (status & 0x80) { /* Byte done */
- outb(*buf++, smbus_base + SMBBLKDAT);
- outb(status, smbus_base + SMBHSTSTAT);
- }
- } while (status & 0x01);
-
- return 0;
-}
-
-
-
static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf)
{
u16 device;
@@ -157,57 +62,6 @@ static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf)
return do_smbus_block_write(res->base, device, cmd, bytes, buf);
}
-static int do_smbus_block_read(unsigned int smbus_base, unsigned int device,
- unsigned int cmd, unsigned int bytes, u8 *buf)
-{
- u8 status;
- int bytes_read = 0;
- if (smbus_wait_until_ready(smbus_base) < 0)
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-
- /* Setup transaction */
- /* Disable interrupts */
- outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
- /* Set the device I'm talking too */
- outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
- /* Set the command/address... */
- outb(cmd & 0xff, smbus_base + SMBHSTCMD);
- /* Set up for a block data read */
- outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2),
- (smbus_base + SMBHSTCTL));
- /* Clear any lingering errors, so the transaction will run */
- outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
-
- /* Start the command */
- outb((inb(smbus_base + SMBHSTCTL) | 0x40),
- smbus_base + SMBHSTCTL);
-
- while (!(inb(smbus_base + SMBHSTSTAT) & 1))
- ;
- /* Poll for transaction completion */
- do {
- status = inb(smbus_base + SMBHSTSTAT);
- if (status & ((1 << 4) | /* FAILED */
- (1 << 3) | /* BUS ERR */
- (1 << 2))) /* DEV ERR */
- return SMBUS_ERROR;
-
- if (status & 0x80) { /* Byte done */
- *buf = inb(smbus_base + SMBBLKDAT);
- buf++;
- bytes_read++;
- outb(status, smbus_base + SMBHSTSTAT);
- if (--bytes == 1) {
- /* indicate that next byte is the last one */
- outb(inb(smbus_base + SMBHSTCTL) | 0x20,
- smbus_base + SMBHSTCTL);
- }
- }
- } while (status & 0x01);
-
- return bytes_read;
-}
-
static int lsmbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buf)
{
u16 device;
diff --git a/src/southbridge/intel/i82801gx/smbus.h b/src/southbridge/intel/i82801gx/smbus.h
deleted file mode 100644
index ff8e1fb112..0000000000
--- a/src/southbridge/intel/i82801gx/smbus.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/smbus_def.h>
-#include "i82801gx.h"
-
-static void smbus_delay(void)
-{
- inb(0x80);
-}
-
-static int smbus_wait_until_ready(u16 smbus_base)
-{
- unsigned int loops = SMBUS_TIMEOUT;
- unsigned char byte;
- do {
- smbus_delay();
- if (--loops == 0)
- break;
- byte = inb(smbus_base + SMBHSTSTAT);
- } while (byte & 1);
- return loops ? 0 : -1;
-}
-
-static int smbus_wait_until_done(u16 smbus_base)
-{
- unsigned int loops = SMBUS_TIMEOUT;
- unsigned char byte;
- do {
- smbus_delay();
- if (--loops == 0)
- break;
- byte = inb(smbus_base + SMBHSTSTAT);
- } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
- return loops ? 0 : -1;
-}
-
-static int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, unsigned int address)
-{
- unsigned char global_status_register;
- unsigned char byte;
-
- if (smbus_wait_until_ready(smbus_base) < 0)
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
- /* Setup transaction */
- /* Disable interrupts */
- outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
- /* Set the device I'm talking too */
- outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
- /* Set the command/address... */
- outb(address & 0xff, smbus_base + SMBHSTCMD);
- /* Set up for a byte data read */
- outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
- (smbus_base + SMBHSTCTL));
- /* Clear any lingering errors, so the transaction will run */
- outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
-
- /* Clear the data byte... */
- outb(0, smbus_base + SMBHSTDAT0);
-
- /* Start the command */
- outb((inb(smbus_base + SMBHSTCTL) | 0x40),
- smbus_base + SMBHSTCTL);
-
- /* Poll for transaction completion */
- if (smbus_wait_until_done(smbus_base) < 0)
- return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
-
- global_status_register = inb(smbus_base + SMBHSTSTAT);
-
- /* Ignore the "In Use" status... */
- global_status_register &= ~(3 << 5);
-
- /* Read results of transaction */
- byte = inb(smbus_base + SMBHSTDAT0);
- if (global_status_register != (1 << 1))
- return SMBUS_ERROR;
- return byte;
-}