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Diffstat (limited to 'src/southbridge/intel/i82801gx')
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c16
2 files changed, 2 insertions, 15 deletions
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 2d3bf24b3e..2cd56e95ff 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -21,6 +21,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
+ select SOUTHBRIDGE_INTEL_COMMON_HPET
if SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 712624c619..74cadc8df4 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -18,6 +18,7 @@
#include <arch/smp/mpspec.h>
#include <string.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
+#include <southbridge/intel/common/hpet.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/spi.h>
@@ -268,21 +269,6 @@ static void i82801gx_rtc_init(struct device *dev)
cmos_init(rtc_failed);
}
-static void enable_hpet(void)
-{
- u32 reg32;
-
- /* Move HPET to default address 0xfed00000 and enable it */
- reg32 = RCBA32(HPTC);
- reg32 |= (1 << 7); // HPET Address Enable
- reg32 &= ~(3 << 0);
- RCBA32(HPTC) = reg32;
- /* On NM10 this only works if read back */
- RCBA32(HPTC);
-
- write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1);
-}
-
static void enable_clock_gating(void)
{
u32 reg32;