diff options
Diffstat (limited to 'src/southbridge/intel/i82801gx/i82801gx_usb_debug.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_usb_debug.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c new file mode 100644 index 0000000000..be524cabaa --- /dev/null +++ b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// An arbitrary address for the BAR +#define EHCI_BAR 0xFEF00000 +// These could be read from DEBUG_BASE (0:1d.7 R 0x5A 16bit) +#define EHCI_BAR_INDEX 0x10 +#define EHCI_DEBUG_OFFSET 0xA0 + +static void set_debug_port(unsigned port) +{ + // Nothing for now? +} + +static void i82801gx_enable_usbdebug_direct(unsigned port) +{ + pci_write_config32(PCI_DEV(0, 0x1d, 7), EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config8(PCI_DEV(0, 0x1d, 7), 0x04, 0x2); // Memory Space Enable +} + |