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Diffstat (limited to 'src/southbridge/intel/i82801ex')
-rw-r--r--src/southbridge/intel/i82801ex/early_smbus.c6
-rw-r--r--src/southbridge/intel/i82801ex/lpc.c18
-rw-r--r--src/southbridge/intel/i82801ex/reset.c4
-rw-r--r--src/southbridge/intel/i82801ex/smbus.h6
-rw-r--r--src/southbridge/intel/i82801ex/watchdog.c34
5 files changed, 34 insertions, 34 deletions
diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c
index 979b8420a5..ad543e7a94 100644
--- a/src/southbridge/intel/i82801ex/early_smbus.c
+++ b/src/southbridge/intel/i82801ex/early_smbus.c
@@ -81,7 +81,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
/* setup transaction */
/* Obtain ownership */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- for(stat=0;(stat&0x40)==0;) {
+ for (stat=0;(stat&0x40)==0;) {
stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
/* clear the done bit */
@@ -105,7 +105,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
SMBUS_IO_BASE + SMBHSTCTL);
- for(i=0;i<length;i++) {
+ for (i=0;i<length;i++) {
/* poll for transaction completion */
if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
@@ -113,7 +113,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
}
/* load the next byte */
- if(i>3)
+ if (i>3)
byte=(data2>>(i%4))&0x0ff;
else
byte=(data1>>(i))&0x0ff;
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index 630484a6de..7d01dbc4ba 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -78,8 +78,8 @@ static void i82801ex_pci_dma_cfg(device_t dev)
#define LPC_EN 0xe6
static void i82801ex_enable_lpc(device_t dev)
{
- /* lpc i/f enable */
- pci_write_config8(dev, LPC_EN, 0x0d);
+ /* lpc i/f enable */
+ pci_write_config8(dev, LPC_EN, 0x0d);
}
typedef struct southbridge_intel_i82801ex_config config_t;
@@ -92,7 +92,7 @@ static void set_i82801ex_gpio_use_sel(
gpio_use_sel = 0x1A003180;
gpio_use_sel2 = 0x00000007;
- for(i = 0; i < 64; i++) {
+ for (i = 0; i < 64; i++) {
int val;
switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) {
case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break;
@@ -121,7 +121,7 @@ static void set_i82801ex_gpio_direction(
gpio_io_sel = 0x0000ffff;
gpio_io_sel2 = 0x00000300;
- for(i = 0; i < 64; i++) {
+ for (i = 0; i < 64; i++) {
int val;
switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) {
case ICH5R_GPIO_SEL_OUTPUT: val = 0; break;
@@ -152,7 +152,7 @@ static void set_i82801ex_gpio_level(
gpio_lvl = 0x1b3f0000;
gpio_blink = 0x00040000;
gpio_lvl2 = 0x00030207;
- for(i = 0; i < 64; i++) {
+ for (i = 0; i < 64; i++) {
int val, blink;
switch(config->gpio[i] & ICH5R_GPIO_LVL_MASK) {
case ICH5R_GPIO_LVL_LOW: val = 0; blink = 0; break;
@@ -184,7 +184,7 @@ static void set_i82801ex_gpio_inv(
int i;
gpio_inv = 0x00000000;
- for(i = 0; i < 32; i++) {
+ for (i = 0; i < 32; i++) {
int val;
switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) {
case ICH5R_GPIO_INV_OFF: val = 0; break;
@@ -205,10 +205,10 @@ static void i82801ex_pirq_init(device_t dev)
/* Get the chip configuration */
config = dev->chip_info;
- if(config->pirq_a_d) {
+ if (config->pirq_a_d) {
pci_write_config32(dev, 0x60, config->pirq_a_d);
}
- if(config->pirq_e_h) {
+ if (config->pirq_e_h) {
pci_write_config32(dev, 0x68, config->pirq_e_h);
}
}
@@ -292,7 +292,7 @@ static void lpc_init(struct device *dev)
/* Clear SATA to non raid */
pci_write_config8(dev, 0xae, 0x00);
- get_option(&pwr_on, "power_on_after_fail");
+ get_option(&pwr_on, "power_on_after_fail");
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {
diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c
index 9936892efe..8036ffde17 100644
--- a/src/southbridge/intel/i82801ex/reset.c
+++ b/src/southbridge/intel/i82801ex/reset.c
@@ -3,6 +3,6 @@
void hard_reset(void)
{
- /* Try rebooting through port 0xcf9 */
- outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+ /* Try rebooting through port 0xcf9 */
+ outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
}
diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h
index b166797600..dbb7b7a416 100644
--- a/src/southbridge/intel/i82801ex/smbus.h
+++ b/src/southbridge/intel/i82801ex/smbus.h
@@ -29,7 +29,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
- } while(byte & 1);
+ } while (byte & 1);
return loops?0:-1;
}
@@ -42,7 +42,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
- } while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
+ } while ((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
return loops?0:-1;
}
@@ -55,7 +55,7 @@ static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
- } while((byte&(1<<7)) == 0);
+ } while ((byte&(1<<7)) == 0);
return loops?0:-1;
}
diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c
index 28e1f5e2f2..6aba2703cb 100644
--- a/src/southbridge/intel/i82801ex/watchdog.c
+++ b/src/southbridge/intel/i82801ex/watchdog.c
@@ -6,23 +6,23 @@
void watchdog_off(void)
{
- device_t dev;
- unsigned long value,base;
+ device_t dev;
+ unsigned long value,base;
/* turn off the ICH5 watchdog */
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
- /* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
- /* Get TCO base */
- base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
- /* Disable the watchdog timer */
- value = inw(base + 0x08);
- value |= 1 << 11;
- outw(value, base + 0x08);
- /* Clear TCO timeout status */
- outw(0x0008, base + 0x04);
- outw(0x0002, base + 0x06);
- printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ /* Enable I/O space */
+ value = pci_read_config16(dev, 0x04);
+ value |= (1 << 10);
+ pci_write_config16(dev, 0x04, value);
+ /* Get TCO base */
+ base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+ /* Disable the watchdog timer */
+ value = inw(base + 0x08);
+ value |= 1 << 11;
+ outw(value, base + 0x08);
+ /* Clear TCO timeout status */
+ outw(0x0008, base + 0x04);
+ outw(0x0002, base + 0x06);
+ printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 06:05:00 +0000