aboutsummaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801dx/smihandler.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/i82801dx/smihandler.c')
-rw-r--r--src/southbridge/intel/i82801dx/smihandler.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 5470890d26..9b0c235d97 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts)
printk(BIOS_DEBUG, "\n");
}
-/* We are using PCIe accesses for now
- * 1. the chipset can do it
- * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-// #include "../../../northbridge/intel/i945/pcie_config.c"
-
int southbridge_io_trap_handler(int smif)
{
switch (smif) {