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path: root/src/southbridge/intel/i82801dx/lpc.c
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Diffstat (limited to 'src/southbridge/intel/i82801dx/lpc.c')
-rw-r--r--src/southbridge/intel/i82801dx/lpc.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 768e70096b..fbf8e12228 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -233,7 +233,7 @@ static void enable_hpet(struct device *dev)
u32 reg32, hpet, val;
/* Set HPET base address and enable it */
- printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_ADDR);
+ printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS);
reg32 = pci_read_config32(dev, GEN_CNTL);
/*
* Bit 17 is HPET enable bit.
@@ -241,7 +241,7 @@ static void enable_hpet(struct device *dev)
*/
reg32 &= ~(3 << 15); /* Clear it */
- hpet = HPET_ADDR >> 12;
+ hpet = CONFIG_HPET_ADDRESS >> 12;
hpet &= 0x3;
reg32 |= (hpet << 15);
@@ -254,7 +254,7 @@ static void enable_hpet(struct device *dev)
val &= 0x7;
if ((val & 0x4) && (hpet == (val & 0x3))) {
- printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_ADDR);
+ printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS);
} else {
printk(BIOS_WARNING, "HPET was not enabled correctly\n");
reg32 &= ~(1 << 17); /* Clear Enable */