summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801db/i82801db.h
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/i82801db/i82801db.h')
-rw-r--r--src/southbridge/intel/i82801db/i82801db.h33
1 files changed, 0 insertions, 33 deletions
diff --git a/src/southbridge/intel/i82801db/i82801db.h b/src/southbridge/intel/i82801db/i82801db.h
deleted file mode 100644
index 9090ea3174..0000000000
--- a/src/southbridge/intel/i82801db/i82801db.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef I82801DB_H
-#define I82801DB_H
-
-#include "chip.h"
-
-extern void i82801db_enable(device_t dev);
-
-#define PCI_DMA_CFG 0x90
-#define SERIRQ_CNTL 0x64
-#define GEN_CNTL 0xd0
-#define GEN_STS 0xd4
-#define RTC_CONF 0xd8
-#define GEN_PMCON_3 0xa4
-
-#endif /* I82801DB_H */