diff options
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/soc.h')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/soc.h | 22 |
1 files changed, 2 insertions, 20 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 1af57b6917..29ed943d3d 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -41,11 +41,8 @@ /* Southbridge internal device MEM BARs (Set to match FSP settings) */ #define DEFAULT_IBASE 0xfed08000 #define DEFAULT_PBASE 0xfed03000 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif + +#include <southbridge/intel/common/rcba.h> #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 @@ -171,21 +168,6 @@ void rangeley_sb_early_initialization(void); #define SMB_SMI_EN (1 << 1) #define HST_EN (1 << 0) -/* Root Complex Register Block */ -#define RCBA 0xf0 -#define RCBA_ENABLE 0x01 - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - /* Root Port configuration space hide */ #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ |