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-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index ec60920ac5..39d4362635 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -19,6 +19,7 @@
#include <lib.h>
#include <timestamp.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <cbmem.h>