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path: root/src/southbridge/intel/fsp_rangeley/gpio.c
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Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/gpio.c')
-rw-r--r--src/southbridge/intel/fsp_rangeley/gpio.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c
index 6ea9c2e7e5..2b3ff9adfd 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.c
+++ b/src/southbridge/intel/fsp_rangeley/gpio.c
@@ -64,7 +64,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
if (gpio->sus.we)
outl(*((u32*)gpio->sus.we), gpiobase + GPIO_SUS_WE);
- /* GPIO PAD settings */
+ /* GPIO PAD Settings */
/* CFIO Core Well Set 1 */
if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) {
write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002);
@@ -100,7 +100,7 @@ int get_gpio(int gpio_num)
int bit;
if (gpio_num > MAX_GPIO_NUMBER)
- return 0; /* Ignore wrong gpio numbers. */
+ return 0; /* Ignore wrong GPIO numbers. */
bit = gpio_num % 32;