diff options
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/early_usb.c')
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/early_usb.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/early_usb.c b/src/southbridge/intel/fsp_rangeley/early_usb.c new file mode 100644 index 0000000000..40759b3387 --- /dev/null +++ b/src/southbridge/intel/fsp_rangeley/early_usb.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include "soc.h" + +#define SOC_EHCI1_TEMP_BAR0 0xe8000000 + +/* + * Setup USB controller MMIO BAR to prevent the + * reference code from resetting the controller. + * + * The BAR will be re-assigned during device + * enumeration so these are only temporary. + */ +void enable_usb_bar(void) +{ + device_t usb0 = SOC_EHCI1_DEV; + u32 cmd; + + /* USB Controller 0 */ + pci_write_config32(usb0, PCI_BASE_ADDRESS_0, + SOC_EHCI1_TEMP_BAR0); + cmd = pci_read_config32(usb0, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb0, PCI_COMMAND, cmd); +} |