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Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/acpi/soc.asl')
-rw-r--r--src/southbridge/intel/fsp_rangeley/acpi/soc.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
index 696a81ae65..b55bd92dd1 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
+++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
@@ -208,7 +208,7 @@ Scope(\)
Offset(0x1000), // Chipset
Offset(0x3000), // Legacy Configuration Registers
Offset(0x3404), // High Performance Timer Configuration
- HPAS, 2, // Address Select
+ HPAS, 2, // Address Select
, 5,
HPTE, 1, // Address Enable
Offset(0x3418), // FD (Function Disable)