diff options
Diffstat (limited to 'src/southbridge/intel/fsp_i89xx/romstage.c')
| -rw-r--r-- | src/southbridge/intel/fsp_i89xx/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index c2b5221c48..385e4d6ba3 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -137,7 +137,7 @@ void main(FSP_INFO_HEADER *fsp_info_header) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); post_code(0x46); if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); boot_mode = 2; /* Clear SLP_TYPE. This will break stage2 but |