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Diffstat (limited to 'src/southbridge/intel/fsp_i89xx/pch.c')
-rw-r--r--src/southbridge/intel/fsp_i89xx/pch.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/pch.c b/src/southbridge/intel/fsp_i89xx/pch.c
index d17aa5bdd8..626791ca1e 100644
--- a/src/southbridge/intel/fsp_i89xx/pch.c
+++ b/src/southbridge/intel/fsp_i89xx/pch.c
@@ -122,9 +122,9 @@ static inline int iobp_poll(void)
/* Check if any port in set X to X+3 is enabled */
-static int pch_pcie_check_set_enabled(device_t dev)
+static int pch_pcie_check_set_enabled(struct device *dev)
{
- device_t port;
+ struct device *port;
int port_func;
int dev_func = PCI_FUNC(dev->path.pci.devfn);
@@ -171,7 +171,7 @@ static void pch_pcie_function_swap(u8 old_fn, u8 new_fn)
/* Update devicetree with new Root Port function number assignment */
static void pch_pcie_devicetree_update(void)
{
- device_t dev;
+ struct device *dev;
/* Update the function numbers in the static devicetree */
for (dev = all_devices; dev; dev = dev->next) {
@@ -200,7 +200,7 @@ static void pch_pcie_devicetree_update(void)
}
/* Special handling for PCIe Root Port devices */
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(struct device *dev)
{
struct southbridge_intel_fsp_i89xx_config *config = dev->chip_info;
u32 reg32;
@@ -307,7 +307,7 @@ static void pch_pcie_enable(device_t dev)
}
}
-void pch_enable(device_t dev)
+void pch_enable(struct device *dev)
{
u32 reg32;