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Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x/finalize.c')
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/finalize.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c
index b81030d3d3..6a8d6f1f06 100644
--- a/src/southbridge/intel/fsp_bd82x6x/finalize.c
+++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c
@@ -52,8 +52,8 @@ void intel_pch_finalize_smm(void)
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);
- pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
- pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+ pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
+ pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
/* Indicate finalize step with post code */
outb(POST_OS_BOOT, 0x80);