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Diffstat (limited to 'src/southbridge/intel/esb6300/reset.c')
-rw-r--r--src/southbridge/intel/esb6300/reset.c27
1 files changed, 0 insertions, 27 deletions
diff --git a/src/southbridge/intel/esb6300/reset.c b/src/southbridge/intel/esb6300/reset.c
deleted file mode 100644
index 77787a5c8f..0000000000
--- a/src/southbridge/intel/esb6300/reset.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ronald G. Minnich
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void hard_reset(void)
-{
- /* Try rebooting through port 0xcf9 */
- outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}