aboutsummaryrefslogtreecommitdiff
path: root/src/southbridge/intel/common
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/common')
-rw-r--r--src/southbridge/intel/common/Kconfig4
-rw-r--r--src/southbridge/intel/common/rcba.h10
2 files changed, 5 insertions, 9 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index a14513dead..5b5fe554e1 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -104,6 +104,10 @@ config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
bool
depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
+config FIXED_RCBA_MMIO_BASE
+ hex
+ default 0xfed1c000
+
config FIXED_SMBUS_IO_BASE
hex
depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS
diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h
index 712a477cc1..4a9847a32a 100644
--- a/src/southbridge/intel/common/rcba.h
+++ b/src/southbridge/intel/common/rcba.h
@@ -3,9 +3,7 @@
#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
-#ifndef __ACPI__
-
-#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#define DEFAULT_RCBA ((u8 *)CONFIG_FIXED_RCBA_MMIO_BASE)
/* Root Complex Register Block */
#define RCBA 0xf0
@@ -23,10 +21,4 @@
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
-#else
-
-#define DEFAULT_RCBA 0xfed1c000
-
-#endif /* __ACPI__ */
-
#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */