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Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c5
-rw-r--r--src/southbridge/intel/bd82x6x/nvs.h9
-rw-r--r--src/southbridge/intel/bd82x6x/smihandler.c6
3 files changed, 9 insertions, 11 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index e41bca260e..80d3a46380 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -12,6 +12,7 @@
#include <arch/io.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
@@ -647,9 +648,9 @@ static void pch_lpc_enable(struct device *dev)
pch_enable(dev);
}
-static void southbridge_inject_dsdt(const struct device *dev)
+void southbridge_inject_dsdt(const struct device *dev)
{
- global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
+ struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) {
memset(gnvs, 0, sizeof(*gnvs));
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index 075eae0921..ae3304ee8e 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -4,7 +4,7 @@
#include <stdint.h>
#include "vendorcode/google/chromeos/gnvs.h"
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -102,9 +102,6 @@ typedef struct global_nvs_t {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
-void acpi_create_gnvs(global_nvs_t *gnvs);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 83799bee1d..b257fb69fb 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -17,8 +17,8 @@
#include "pch.h"
#include "nvs.h"
-static global_nvs_t *gnvs;
-global_nvs_t *smm_get_gnvs(void)
+static struct global_nvs *gnvs;
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -196,7 +196,7 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
smi_apmc_find_state_save(apm_cnt);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((u32)state->rbx);
+ gnvs = (struct global_nvs *)((u32)state->rbx);
*smm_done = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}