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path: root/src/southbridge/intel/bd82x6x/smihandler.c
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Diffstat (limited to 'src/southbridge/intel/bd82x6x/smihandler.c')
-rw-r--r--src/southbridge/intel/bd82x6x/smihandler.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 420c5db211..093da5c60a 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -326,6 +326,17 @@ static void southbridge_gate_memory_reset(void)
outl(reg32, gpiobase + GP_LVL2);
}
+static void xhci_sleep(u8 slp_typ)
+{
+ u32 reg32;
+
+ if (slp_typ == SLP_TYP_S5) {
+ reg32 = pcie_read_config32(PCH_XHCI_DEV, 0x74);
+ reg32 |= (1 << 8 | 0x03 );
+ pcie_write_config32(PCH_XHCI_DEV, 0x74, reg32);
+ }
+}
+
static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
{
u8 reg8;
@@ -353,6 +364,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
slp_typ = (reg32 >> 10) & 7;
+ if (smm_get_gnvs()->xhci)
+ xhci_sleep(slp_typ);
+
/* Do any mainboard sleep handling */
tseg_relocate((void **)&mainboard_sleep);
if (mainboard_sleep)