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path: root/src/southbridge/intel/bd82x6x/pch.h
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Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index ac2d036f37..ebcb058c0b 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -68,7 +68,6 @@ int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-void gpi_route_interrupt(u8 gpi, u8 mode);
#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
@@ -104,14 +103,6 @@ early_usb_init (const struct southbridge_usb_port *portmap);
int rtc_failure(void);
#endif
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON 1
-#define MAINBOARD_POWER_KEEP 2
-
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
/* PM I/O Space */
#define UPRWC 0x3c
#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */