diff options
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.c | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 00d5e12408..7b0662b4fe 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -301,7 +301,6 @@ static void pch_pcie_devicetree_update( static void pch_pcie_enable(struct device *dev) { struct southbridge_intel_bd82x6x_config *config = dev->chip_info; - u16 reg16; if (!config) return; @@ -345,9 +344,7 @@ static void pch_pcie_enable(struct device *dev) /* Handle workaround for PPT and CPT/B1+ */ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) && !pch_pcie_check_set_enabled(dev)) { - u8 reg8 = pci_read_config8(dev, 0xe2); - reg8 |= 1; - pci_write_config8(dev, 0xe2, reg8); + pci_or_config8(dev, 0xe2, 1); } /* @@ -358,10 +355,8 @@ static void pch_pcie_enable(struct device *dev) } /* Ensure memory, io, and bus master are all disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Do not claim downstream transactions for PCIe ports */ new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); @@ -408,8 +403,6 @@ static void pch_pcie_enable(struct device *dev) void pch_enable(struct device *dev) { - u16 reg16; - /* PCH PCIe Root Ports get special handling */ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) return pch_pcie_enable(dev); @@ -418,10 +411,8 @@ void pch_enable(struct device *dev) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Hide this device if possible */ pch_hide_devfn(dev->path.pci.devfn); |