aboutsummaryrefslogtreecommitdiff
path: root/src/southbridge/intel/bd82x6x/me.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/bd82x6x/me.c')
-rw-r--r--src/southbridge/intel/bd82x6x/me.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index ebb9db93e5..40b0cc2bd8 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -438,7 +438,6 @@ static void intel_me7_finalize_smm(void)
{
struct me_hfs hfs;
u32 reg32;
- u16 reg16;
mei_base_address = (u32 *)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
@@ -461,10 +460,8 @@ static void intel_me7_finalize_smm(void)
mkhi_end_of_post();
/* Make sure IO is disabled */
- reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND);
- reg16 &= ~(PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16);
+ pci_and_config16(PCH_ME_DEV, PCI_COMMAND,
+ ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
/* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);