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Diffstat (limited to 'src/southbridge/intel/bd82x6x/early_me.c')
-rw-r--r--src/southbridge/intel/bd82x6x/early_me.c129
1 files changed, 97 insertions, 32 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index b7dbf3439f..ed9351fc16 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -44,13 +44,6 @@ static inline void pci_read_dword_ptr(void *ptr, int offset)
memcpy(ptr, &dword, sizeof(dword));
}
-static inline void pci_write_dword_ptr(void *ptr, int offset)
-{
- u32 dword = 0;
- memcpy(&dword, ptr, sizeof(dword));
- pci_write_config32(PCH_ME_DEV, offset, dword);
-}
-
void intel_early_me_status(void)
{
struct me_hfs hfs;
@@ -125,64 +118,136 @@ static inline void set_global_reset(int enable)
int intel_early_me_init_done(u8 status)
{
- u8 reset;
- int count;
+ u8 reset, errorcode, opmode;
+ u16 reg16;
u32 mebase_l, mebase_h;
- struct me_hfs hfs;
+ u32 millisec;
+ u32 hfs, me_fws2;
struct me_did did = {
.init_done = ME_INIT_DONE,
.status = status
};
+ u32 meDID;
+
+ hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xff000) >> 12;
+
+ opmode = (hfs & 0xf0) >> 4;
+ errorcode = hfs & 0xf;
+
+ if (opmode != ME_HFS_MODE_NORMAL) {
+ printk(BIOS_NOTICE, "ME: Wrong mode : %d\n", opmode);
+ //return 0;
+ }
+ if (errorcode) {
+ printk(BIOS_NOTICE, "ME: HFS error : %d\n", errorcode);
+ //return 0;
+ }
+
+ me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
+ printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
+ printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
+ printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
+ printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
+ printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
+ printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
+ printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
+ printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
+ printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
+ printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
+ printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
+ printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
+ printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
+ printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
+ printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
+
+ // Poll cpu replaced for 50ms
+ millisec = 0;
+ while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) {
+ udelay(1000);
+ me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
+ millisec++;
+ }
+ if (millisec >= 50 || ((me_fws2 & 0x100) >> 8) == 0x0) {
+ printk(BIOS_NOTICE, "Waited long enough, or CPU was not replaced, continue...\n");
+ } else if ((me_fws2 & 0x100) == 0x100) {
+ if ((me_fws2 & 0x80) == 0x80) {
+ printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
+ reg16 = pcie_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80;
+ pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
+ set_global_reset(0);
+ outb(0x6, 0xcf9);
+ halt();
+ }
+
+ if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {
+ printk(BIOS_NOTICE, "Full training required\n");
+ }
+ }
+
+ printk(BIOS_NOTICE, "PASSED! Tell ME that DRAM is ready\n");
/* MEBASE from MESEG_BASE[35:20] */
mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
- /* Send message to ME */
- printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, "
- "UMA base: 0x%04x\n", status, did.uma_base);
+ meDID = did.uma_base | (1 << 28);// | (1 << 23);
+ pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID);
- pci_write_dword_ptr(&did, PCI_ME_H_GS);
+ udelay(1100);
/* Must wait for ME acknowledgement */
- for (count = ME_RETRY; count > 0; --count) {
- pci_read_dword_ptr(&hfs, PCI_ME_HFS);
- if (hfs.bios_msg_ack)
- break;
- udelay(ME_DELAY);
- }
- if (!count) {
- printk(BIOS_ERR, "ERROR: ME failed to respond\n");
- return -1;
+ millisec = 0;
+ hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
+ while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) {
+ udelay(1000);
+ hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
+ millisec++;
}
+ me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
+ printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
+ printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
+ printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
+ printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
+ printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
+ printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
+ printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
+ printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
+ printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
+ printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
+ printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
+ printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
+ printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
+ printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
+ printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
+
+
/* Return the requested BIOS action */
printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
- me_ack_values[hfs.ack_data]);
-
- /* Check status after acknowledgement */
- intel_early_me_status();
+ me_ack_values[(hfs & 0xe) >> 1]);
- reset = 0;
- switch (hfs.ack_data) {
+ reset = inb(0xcf9);
+ reset &= 0xf1;
+ switch ((hfs & 0xe) >> 1) {
+ case ME_HFS_ACK_NO_DID:
case ME_HFS_ACK_CONTINUE:
/* Continue to boot */
return 0;
case ME_HFS_ACK_RESET:
/* Non-power cycle reset */
set_global_reset(0);
- reset = 0x06;
+ reset |= 0x06;
break;
case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */
set_global_reset(0);
- reset = 0x0e;
+ reset |= 0x0e;
break;
case ME_HFS_ACK_GBL_RESET:
/* Global reset */
set_global_reset(1);
- reset = 0x0e;
+ reset |= 0x0e;
break;
case ME_HFS_ACK_S3:
case ME_HFS_ACK_S4:
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-21 09:08:00 +0000