aboutsummaryrefslogtreecommitdiff
path: root/src/southbridge/intel/bd82x6x/acpi/pch.asl
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/bd82x6x/acpi/pch.asl')
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/pch.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl
index 9f5033d759..a068bc039c 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pch.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl
@@ -202,7 +202,7 @@ Scope(\)
Offset(0x1000), // Chipset
Offset(0x3000), // Legacy Configuration Registers
Offset(0x3404), // High Performance Timer Configuration
- HPAS, 2, // Address Select
+ HPAS, 2, // Address Select
, 5,
HPTE, 1, // Address Enable
Offset(0x3418), // FD (Function Disable)