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-rw-r--r--src/southbridge/broadcom/bcm21000/pcie.c2
-rw-r--r--src/southbridge/broadcom/bcm5780/nic.c12
-rw-r--r--src/southbridge/broadcom/bcm5780/pcie.c16
-rw-r--r--src/southbridge/broadcom/bcm5780/pcix.c20
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785.c14
-rw-r--r--src/southbridge/broadcom/bcm5785/chip.h8
-rw-r--r--src/southbridge/broadcom/bcm5785/early_setup.c236
-rw-r--r--src/southbridge/broadcom/bcm5785/early_smbus.c8
-rw-r--r--src/southbridge/broadcom/bcm5785/ide.c16
-rw-r--r--src/southbridge/broadcom/bcm5785/lpc.c30
-rw-r--r--src/southbridge/broadcom/bcm5785/reset.c24
-rw-r--r--src/southbridge/broadcom/bcm5785/sata.c32
-rw-r--r--src/southbridge/broadcom/bcm5785/sb_pci_main.c98
-rw-r--r--src/southbridge/broadcom/bcm5785/smbus.h110
-rw-r--r--src/southbridge/broadcom/bcm5785/usb.c8
15 files changed, 317 insertions, 317 deletions
diff --git a/src/southbridge/broadcom/bcm21000/pcie.c b/src/southbridge/broadcom/bcm21000/pcie.c
index ca9a2253ea..ab52029729 100644
--- a/src/southbridge/broadcom/bcm21000/pcie.c
+++ b/src/southbridge/broadcom/bcm21000/pcie.c
@@ -43,7 +43,7 @@ static void pcie_init(struct device *dev)
}
static struct pci_operations lops_pci = {
- .set_subsystem = 0,
+ .set_subsystem = 0,
};
static struct device_operations pcie_ops = {
diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c
index be23d688c9..d0ff9ca162 100644
--- a/src/southbridge/broadcom/bcm5780/nic.c
+++ b/src/southbridge/broadcom/bcm5780/nic.c
@@ -23,12 +23,12 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations nic_ops = {
@@ -47,7 +47,7 @@ static const struct pci_driver nic_driver __pci_driver = {
};
static const struct pci_driver nic1_driver __pci_driver = {
- .ops = &nic_ops,
- .vendor = PCI_VENDOR_ID_BROADCOM,
- .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1,
+ .ops = &nic_ops,
+ .vendor = PCI_VENDOR_ID_BROADCOM,
+ .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1,
};
diff --git a/src/southbridge/broadcom/bcm5780/pcie.c b/src/southbridge/broadcom/bcm5780/pcie.c
index 6f8493eadc..2ed6102bec 100644
--- a/src/southbridge/broadcom/bcm5780/pcie.c
+++ b/src/southbridge/broadcom/bcm5780/pcie.c
@@ -35,17 +35,17 @@ static void pcie_init(struct device *dev)
}
static struct pci_operations lops_pci = {
- .set_subsystem = 0,
+ .set_subsystem = 0,
};
static struct device_operations pcie_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pcie_init,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pcie_init,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
};
diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c
index 22dc771bab..8aa37a6757 100644
--- a/src/southbridge/broadcom/bcm5780/pcix.c
+++ b/src/southbridge/broadcom/bcm5780/pcix.c
@@ -22,22 +22,22 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations ht_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = 0 ,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = 0 ,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
};
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index efe38ab3ac..d9a12686a4 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -36,17 +36,17 @@ void bcm5785_enable(device_t dev)
sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
} else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
- (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
- {
- unsigned devfn;
- devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
- sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn);
+ (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
+ {
+ unsigned devfn;
+ devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
+ sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn);
// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
- }
+ }
else { // same bus
unsigned devfn;
devfn = (dev->path.pci.devfn) & ~7;
- if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
+ if ( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
if (dev->device == 0x0036) //PCI-X Bridge
{ devfn += (1<<3); }
else if (dev->device == 0x0223) // USB
diff --git a/src/southbridge/broadcom/bcm5785/chip.h b/src/southbridge/broadcom/bcm5785/chip.h
index ac39fd1e31..2c6573439c 100644
--- a/src/southbridge/broadcom/bcm5785/chip.h
+++ b/src/southbridge/broadcom/bcm5785/chip.h
@@ -19,10 +19,10 @@
struct southbridge_broadcom_bcm5785_config
{
- unsigned int ide0_enable : 1;
- unsigned int ide1_enable : 1;
- unsigned int sata0_enable : 1;
- unsigned int sata1_enable : 1;
+ unsigned int ide0_enable : 1;
+ unsigned int ide1_enable : 1;
+ unsigned int sata0_enable : 1;
+ unsigned int sata1_enable : 1;
};
#endif /* BCM5785_CHIP_H */
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index 3ddc9ca643..8aba58cf75 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -19,62 +19,62 @@
static void bcm5785_enable_lpc(void)
{
- uint8_t byte;
- device_t dev;
-
- dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
-
- /* LPC Control 0 */
- byte = pci_read_config8(dev, 0x44);
- /* Serial 0 */
- byte |= (1<<6);
- pci_write_config8(dev, 0x44, byte);
-
- /* LPC Control 4 */
- byte = pci_read_config8(dev, 0x48);
- /* superio port 0x2e/4e enable */
- byte |=(1<<1)|(1<<0);
- pci_write_config8(dev, 0x48, byte);
+ uint8_t byte;
+ device_t dev;
+
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+
+ /* LPC Control 0 */
+ byte = pci_read_config8(dev, 0x44);
+ /* Serial 0 */
+ byte |= (1<<6);
+ pci_write_config8(dev, 0x44, byte);
+
+ /* LPC Control 4 */
+ byte = pci_read_config8(dev, 0x48);
+ /* superio port 0x2e/4e enable */
+ byte |=(1<<1)|(1<<0);
+ pci_write_config8(dev, 0x48, byte);
}
static void bcm5785_enable_wdt_port_cf9(void)
{
- device_t dev;
- uint32_t dword;
- uint32_t dword_old;
+ device_t dev;
+ uint32_t dword;
+ uint32_t dword_old;
- dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
- dword_old = pci_read_config32(dev, 0x4c);
- dword = dword_old | (1<<4); //enable Timer Func
- if (dword != dword_old ) {
- pci_write_config32(dev, 0x4c, dword);
- }
+ dword_old = pci_read_config32(dev, 0x4c);
+ dword = dword_old | (1<<4); //enable Timer Func
+ if (dword != dword_old ) {
+ pci_write_config32(dev, 0x4c, dword);
+ }
- dword_old = pci_read_config32(dev, 0x6c);
- dword = dword_old | (1<<9); //unhide Timer Func in pci space
- if (dword != dword_old ) {
- pci_write_config32(dev, 0x6c, dword);
- }
+ dword_old = pci_read_config32(dev, 0x6c);
+ dword = dword_old | (1<<9); //unhide Timer Func in pci space
+ if (dword != dword_old ) {
+ pci_write_config32(dev, 0x6c, dword);
+ }
- dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
- /* enable cf9 */
- pci_write_config8(dev, 0x40, (1<<2));
+ /* enable cf9 */
+ pci_write_config8(dev, 0x40, (1<<2));
}
unsigned get_sbdn(unsigned bus)
{
- device_t dev;
+ device_t dev;
- /* Find the device.
- * There can only be one bcm5785 on a hypertransport chain/bus.
- */
- dev = pci_locate_device_on_bus(
- PCI_ID(0x1166, 0x0036),
- bus);
+ /* Find the device.
+ * There can only be one bcm5785 on a hypertransport chain/bus.
+ */
+ dev = pci_locate_device_on_bus(
+ PCI_ID(0x1166, 0x0036),
+ bus);
- return (dev>>15) & 0x1f;
+ return (dev>>15) & 0x1f;
}
@@ -89,8 +89,8 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
// set port to 0x2060
outb(0x67, 0xcd6);
outb(0x60, 0xcd7);
- outb(0x68, 0xcd6);
- outb(0x20, 0xcd7);
+ outb(0x68, 0xcd6);
+ outb(0x20, 0xcd7);
outb(0x69, 0xcd6);
outb(7, 0xcd7);
@@ -107,113 +107,113 @@ void ldtstop_sb(void)
void hard_reset(void)
{
- bcm5785_enable_wdt_port_cf9();
+ bcm5785_enable_wdt_port_cf9();
- set_bios_reset();
+ set_bios_reset();
- /* full reset */
- outb(0x0a, 0x0cf9);
- outb(0x0e, 0x0cf9);
+ /* full reset */
+ outb(0x0a, 0x0cf9);
+ outb(0x0e, 0x0cf9);
}
void soft_reset(void)
{
- bcm5785_enable_wdt_port_cf9();
+ bcm5785_enable_wdt_port_cf9();
- set_bios_reset();
+ set_bios_reset();
#if 1
- /* link reset */
-// outb(0x02, 0x0cf9);
- outb(0x06, 0x0cf9);
+ /* link reset */
+// outb(0x02, 0x0cf9);
+ outb(0x06, 0x0cf9);
#endif
}
static void bcm5785_enable_msg(void)
{
- device_t dev;
- uint32_t dword;
- uint32_t dword_old;
- uint8_t byte;
-
- dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
-
- byte = pci_read_config8(dev, 0x42);
- byte = (1<<1); //enable a20
- pci_write_config8(dev, 0x42, byte);
-
- dword_old = pci_read_config32(dev, 0x6c);
- // bit 5: enable A20 Message
- // bit 4: enable interrupt messages
- // bit 3: enable reset init message
- // bit 2: enable keyboard init message
- // bit 1: enable upsteam messages
- // bit 0: enable shutdowm message to init generation
- dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
- if (dword != dword_old ) {
- pci_write_config32(dev, 0x6c, dword);
- }
+ device_t dev;
+ uint32_t dword;
+ uint32_t dword_old;
+ uint8_t byte;
+
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+
+ byte = pci_read_config8(dev, 0x42);
+ byte = (1<<1); //enable a20
+ pci_write_config8(dev, 0x42, byte);
+
+ dword_old = pci_read_config32(dev, 0x6c);
+ // bit 5: enable A20 Message
+ // bit 4: enable interrupt messages
+ // bit 3: enable reset init message
+ // bit 2: enable keyboard init message
+ // bit 1: enable upsteam messages
+ // bit 0: enable shutdowm message to init generation
+ dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
+ if (dword != dword_old ) {
+ pci_write_config32(dev, 0x6c, dword);
+ }
}
static void bcm5785_early_setup(void)
{
- uint8_t byte;
- uint32_t dword;
- device_t dev;
+ uint8_t byte;
+ uint32_t dword;
+ device_t dev;
//F0
- // enable device on bcm5785 at first
- dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
- dword = pci_read_config32(dev, 0x64);
- dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable
- dword |= (1<<8); // USB enable
- dword |= /* (1<<27)|*/(1<<14); // IDE enable
- pci_write_config32(dev, 0x64, dword);
-
- byte = pci_read_config8(dev, 0x84);
- byte |= (1<<0); // SATA enable
- pci_write_config8(dev, 0x84, byte);
+ // enable device on bcm5785 at first
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+ dword = pci_read_config32(dev, 0x64);
+ dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable
+ dword |= (1<<8); // USB enable
+ dword |= /* (1<<27)|*/(1<<14); // IDE enable
+ pci_write_config32(dev, 0x64, dword);
+
+ byte = pci_read_config8(dev, 0x84);
+ byte |= (1<<0); // SATA enable
+ pci_write_config8(dev, 0x84, byte);
// WDT and cf9 for later in ramstage to call hard_reset
- bcm5785_enable_wdt_port_cf9();
+ bcm5785_enable_wdt_port_cf9();
- bcm5785_enable_msg();
+ bcm5785_enable_msg();
// IDE related
//F0
- byte = pci_read_config8(dev, 0x4e);
- byte |= (1<<4); //enable IDE ext regs
- pci_write_config8(dev, 0x4e, byte);
+ byte = pci_read_config8(dev, 0x4e);
+ byte |= (1<<4); //enable IDE ext regs
+ pci_write_config8(dev, 0x4e, byte);
//F1
- dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
- byte = pci_read_config8(dev, 0x48);
- byte &= ~1; // disable pri channel
- pci_write_config8(dev, 0x48, byte);
- pci_write_config8(dev, 0xb0, 0x01);
- pci_write_config8(dev, 0xb2, 0x02);
- byte = pci_read_config8(dev, 0x06);
- byte |= (1<<4); // so b0, b2 can not be changed from now
- pci_write_config8(dev, 0x06, byte);
- byte = pci_read_config8(dev, 0x49);
- byte |= 1; // enable second channel
- pci_write_config8(dev, 0x49, byte);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
+ byte = pci_read_config8(dev, 0x48);
+ byte &= ~1; // disable pri channel
+ pci_write_config8(dev, 0x48, byte);
+ pci_write_config8(dev, 0xb0, 0x01);
+ pci_write_config8(dev, 0xb2, 0x02);
+ byte = pci_read_config8(dev, 0x06);
+ byte |= (1<<4); // so b0, b2 can not be changed from now
+ pci_write_config8(dev, 0x06, byte);
+ byte = pci_read_config8(dev, 0x49);
+ byte |= 1; // enable second channel
+ pci_write_config8(dev, 0x49, byte);
//F2
- dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
- byte = pci_read_config8(dev, 0x40);
- byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
- pci_write_config8(dev, 0x40, byte);
+ byte = pci_read_config8(dev, 0x40);
+ byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
+ pci_write_config8(dev, 0x40, byte);
- pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
+ pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
// USB related
- pci_write_config8(dev, 0x90, 0x40);
- pci_write_config8(dev, 0x92, 0x06);
- pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
- pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
- pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
- pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
- pci_write_config8(dev, 0xb4, 0x40);
+ pci_write_config8(dev, 0x90, 0x40);
+ pci_write_config8(dev, 0x92, 0x06);
+ pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
+ pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
+ pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
+ pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
+ pci_write_config8(dev, 0xb4, 0x40);
}
diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c
index 9d3d3e8898..f37aed98a4 100644
--- a/src/southbridge/broadcom/bcm5785/early_smbus.c
+++ b/src/southbridge/broadcom/bcm5785/early_smbus.c
@@ -38,20 +38,20 @@ static void enable_smbus(void)
static inline int smbus_recv_byte(unsigned device)
{
- return do_smbus_recv_byte(SMBUS_IO_BASE, device);
+ return do_smbus_recv_byte(SMBUS_IO_BASE, device);
}
static inline int smbus_send_byte(unsigned device, unsigned char val)
{
- return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
+ return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
}
static inline int smbus_read_byte(unsigned device, unsigned address)
{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
- return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
+ return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
}
diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c
index 868586c02b..a6bb20421c 100644
--- a/src/southbridge/broadcom/bcm5785/ide.c
+++ b/src/southbridge/broadcom/bcm5785/ide.c
@@ -23,13 +23,13 @@
static void bcm5785_ide_read_resources(device_t dev)
{
- /* Get the normal pci resources of this device */
- pci_dev_read_resources(dev);
+ /* Get the normal pci resources of this device */
+ pci_dev_read_resources(dev);
- /* BAR */
- pci_get_resource(dev, 0x64);
+ /* BAR */
+ pci_get_resource(dev, 0x64);
- compact_resources(dev);
+ compact_resources(dev);
}
static void ide_init(struct device *dev)
@@ -38,12 +38,12 @@ static void ide_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations ide_ops = {
diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
index f0d74169c4..59ba798756 100644
--- a/src/southbridge/broadcom/bcm5785/lpc.c
+++ b/src/southbridge/broadcom/bcm5785/lpc.c
@@ -74,15 +74,15 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
reg = pci_read_config8(dev, 0x44);
for (link = dev->link_list; link; link = link->next) {
- device_t child;
- for (child = link->children; child; child = child->sibling) {
- if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
+ device_t child;
+ for (child = link->children; child; child = child->sibling) {
+ if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
- for(res = child->resource_list; res; res = res->next) {
- unsigned long base, end; // don't need long long
- if(!(res->flags & IORESOURCE_IO)) continue;
- base = res->base;
- end = resource_end(res);
+ for (res = child->resource_list; res; res = res->next) {
+ unsigned long base, end; // don't need long long
+ if (!(res->flags & IORESOURCE_IO)) continue;
+ base = res->base;
+ end = resource_end(res);
printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
switch(base) {
case 0x60: //KBC
@@ -103,8 +103,8 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
}
}
}
- }
- }
+ }
+ }
pci_write_config32(dev, 0x44, reg);
@@ -112,18 +112,18 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
static void bcm5785_lpc_enable_resources(device_t dev)
{
- pci_dev_enable_resources(dev);
- bcm5785_lpc_enable_childrens_resources(dev);
+ pci_dev_enable_resources(dev);
+ bcm5785_lpc_enable_childrens_resources(dev);
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations lpc_ops = {
diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c
index 7064b19e65..8140e014c2 100644
--- a/src/southbridge/broadcom/bcm5785/reset.c
+++ b/src/southbridge/broadcom/bcm5785/reset.c
@@ -18,24 +18,24 @@
#include <reset.h>
#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFFF) << 20) | \
- (((DEV) & 0x1F) << 15) | \
- (((FN) & 0x7) << 12))
+ (((BUS) & 0xFFF) << 20) | \
+ (((DEV) & 0x1F) << 15) | \
+ (((FN) & 0x7) << 12))
static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
+ unsigned addr;
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ outl(value, 0xCFC);
}
static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
+ unsigned addr;
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ return inl(0xCFC);
}
#include "../../../northbridge/amd/amdk8/reset_test.c"
@@ -43,7 +43,7 @@ static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
void hard_reset(void)
{
set_bios_reset();
- /* Try rebooting through port 0xcf9 */
+ /* Try rebooting through port 0xcf9 */
/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c
index 75f2d46616..02331d9007 100644
--- a/src/southbridge/broadcom/bcm5785/sata.c
+++ b/src/southbridge/broadcom/bcm5785/sata.c
@@ -28,41 +28,41 @@ static void sata_init(struct device *dev)
uint8_t byte;
u8 *mmio;
- struct resource *res;
- u8 *mmio_base;
+ struct resource *res;
+ u8 *mmio_base;
int i;
- if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
+ if (!(dev->path.pci.devfn & 7)) { // only set it in Func0
byte = pci_read_config8(dev, 0x78);
byte |= (1<<7);
- pci_write_config8(dev, 0x78, byte);
+ pci_write_config8(dev, 0x78, byte);
res = find_resource(dev, 0x24);
- mmio_base = res2mmio(res, 0, 3);
+ mmio_base = res2mmio(res, 0, 3);
write32(mmio_base + 0x10f0, 0x40000001);
write32(mmio_base + 0x8c, 0x00ff2007);
- mdelay( 10 );
+ mdelay( 10 );
write32(mmio_base + 0x8c, 0x78592009);
- mdelay( 10 );
+ mdelay( 10 );
write32(mmio_base + 0x8c, 0x00082004);
- mdelay( 10 );
+ mdelay( 10 );
write32(mmio_base + 0x8c, 0x00002004);
- mdelay( 10 );
+ mdelay( 10 );
//init PHY
printk(BIOS_DEBUG, "init PHY...\n");
- for(i=0; i<4; i++) {
+ for (i=0; i<4; i++) {
mmio = (u8 *)(uintptr_t)(res->base + 0x100 * i);
byte = read8(mmio + 0x40);
printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
- if(byte & 0x4) {// bit 2 is set
+ if (byte & 0x4) {// bit 2 is set
byte = read8(mmio+0x48);
write8(mmio + 0x48, byte | 1);
write8(mmio + 0x48, byte & (~1));
- byte = read8(mmio + 0x40);
- printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
+ byte = read8(mmio + 0x40);
+ printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
}
}
}
@@ -70,12 +70,12 @@ static void sata_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations sata_ops = {
diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
index 1898ca627a..ab0cd05786 100644
--- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c
+++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
@@ -45,7 +45,7 @@ static void sb_init(device_t dev)
} else {
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
}
- if( byte != byte_old) {
+ if ( byte != byte_old) {
outb(byte, 0x70);
}
@@ -63,101 +63,101 @@ static void bcm5785_sb_read_resources(device_t dev)
compact_resources(dev);
- /* Add an extra subtractive resource for both memory and I/O */
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ /* Add an extra subtractive resource for both memory and I/O */
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static int lsmbus_recv_byte(device_t dev)
{
- unsigned device;
- struct resource *res;
+ unsigned device;
+ struct resource *res;
struct bus *pbus;
- device = dev->path.i2c.device;
+ device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_recv_byte(res->base, device);
+ return do_smbus_recv_byte(res->base, device);
}
static int lsmbus_send_byte(device_t dev, uint8_t val)
{
- unsigned device;
- struct resource *res;
- struct bus *pbus;
+ unsigned device;
+ struct resource *res;
+ struct bus *pbus;
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_send_byte(res->base, device, val);
+ return do_smbus_send_byte(res->base, device, val);
}
static int lsmbus_read_byte(device_t dev, uint8_t address)
{
- unsigned device;
- struct resource *res;
- struct bus *pbus;
+ unsigned device;
+ struct resource *res;
+ struct bus *pbus;
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_read_byte(res->base, device, address);
+ return do_smbus_read_byte(res->base, device, address);
}
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
{
- unsigned device;
- struct resource *res;
- struct bus *pbus;
+ unsigned device;
+ struct resource *res;
+ struct bus *pbus;
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_write_byte(res->base, device, address, val);
+ return do_smbus_write_byte(res->base, device, address, val);
}
static struct smbus_bus_operations lops_smbus_bus = {
- .recv_byte = lsmbus_recv_byte,
- .send_byte = lsmbus_send_byte,
- .read_byte = lsmbus_read_byte,
- .write_byte = lsmbus_write_byte,
+ .recv_byte = lsmbus_recv_byte,
+ .send_byte = lsmbus_send_byte,
+ .read_byte = lsmbus_read_byte,
+ .write_byte = lsmbus_write_byte,
};
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x2c,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x2c,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations sb_ops = {
- .read_resources = bcm5785_sb_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = sb_init,
- .scan_bus = scan_smbus,
+ .read_resources = bcm5785_sb_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = sb_init,
+ .scan_bus = scan_smbus,
// .enable = bcm5785_enable,
- .ops_pci = &lops_pci,
- .ops_smbus_bus = &lops_smbus_bus,
+ .ops_pci = &lops_pci,
+ .ops_smbus_bus = &lops_smbus_bus,
};
static const struct pci_driver sb_driver __pci_driver = {
- .ops = &sb_ops,
- .vendor = PCI_VENDOR_ID_SERVERWORKS,
- .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN,
+ .ops = &sb_ops,
+ .vendor = PCI_VENDOR_ID_SERVERWORKS,
+ .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN,
};
diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h
index bb43269b9b..76c593ba19 100644
--- a/src/southbridge/broadcom/bcm5785/smbus.h
+++ b/src/southbridge/broadcom/bcm5785/smbus.h
@@ -53,7 +53,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
return 0;
}
outb(val, smbus_io_base + SMBHSTSTAT);
- } while(--loops);
+ } while (--loops);
return -2; // time out
}
@@ -73,7 +73,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
outb(val, smbus_io_base + SMBHSTSTAT); // clear status
return 0; //
}
- } while(--loops);
+ } while (--loops);
return -3; // timeout
}
@@ -81,54 +81,54 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
{
uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; // not ready
- }
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; // not ready
+ }
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; // Clear [4:2]
- byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
- outb(byte, smbus_io_base + SMBHSTCTRL);
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; // Clear [4:2]
+ byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+ outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; // timeout or error
- }
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; // timeout or error
+ }
- /* read results of transaction */
- byte = inb(smbus_io_base + SMBHSTCMD);
+ /* read results of transaction */
+ byte = inb(smbus_io_base + SMBHSTCMD);
return byte;
}
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
{
- uint8_t byte;
+ uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; // not ready
- }
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; // not ready
+ }
- /* set the command... */
- outb(val, smbus_io_base + SMBHSTCMD);
+ /* set the command... */
+ outb(val, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; // Clear [4:2]
- byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
- outb(byte, smbus_io_base + SMBHSTCTRL);
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; // Clear [4:2]
+ byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+ outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; // timeout or error
- }
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; // timeout or error
+ }
- return 0;
+ return 0;
}
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
@@ -142,8 +142,8 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
/* set the command/address... */
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
byte = inb(smbus_io_base + SMBHSTCTRL);
byte &= 0xe3; // Clear [4:2]
@@ -163,30 +163,30 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
{
- uint8_t byte;
+ uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; // not ready
- }
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; // not ready
+ }
- /* set the command/address... */
- outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+ /* set the command/address... */
+ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
- /* output value */
- outb(val, smbus_io_base + SMBHSTDAT0);
+ /* output value */
+ outb(val, smbus_io_base + SMBHSTDAT0);
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; // Clear [4:2]
- byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
- outb(byte, smbus_io_base + SMBHSTCTRL);
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; // Clear [4:2]
+ byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
+ outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; // timeout or error
- }
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; // timeout or error
+ }
- return 0;
+ return 0;
}
diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c
index fa73b2f1aa..9aa64df842 100644
--- a/src/southbridge/broadcom/bcm5785/usb.c
+++ b/src/southbridge/broadcom/bcm5785/usb.c
@@ -23,7 +23,7 @@
static void usb_init(struct device *dev)
{
- uint32_t dword;
+ uint32_t dword;
dword = pci_read_config32(dev, 0x04);
dword |= (1<<2)|(1<<1)|(1<<0);
@@ -35,12 +35,12 @@ static void usb_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations usb_ops = {
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 00:24:01 +0000