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-rw-r--r--src/southbridge/amd/agesa/hudson/Makefile.inc1
-rw-r--r--src/southbridge/amd/agesa/hudson/hudson.h3
-rw-r--r--src/southbridge/amd/agesa/hudson/resume.c128
3 files changed, 132 insertions, 0 deletions
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
index d50d09ebef..6a097fccac 100644
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ b/src/southbridge/amd/agesa/hudson/Makefile.inc
@@ -17,6 +17,7 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_setup.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
+ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c
# ROMSIG At ROMBASE + 0x20000:
# +-----------+---------------+----------------+------------+
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h
index 686dbb5e31..e8f80aaf4e 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.h
+++ b/src/southbridge/amd/agesa/hudson/hudson.h
@@ -21,6 +21,7 @@
#define HUDSON_H
#include <device/pci_ids.h>
+#include <device/device.h>
#include "chip.h"
/* Power management index/data registers */
@@ -69,6 +70,8 @@ int acpi_is_wakeup_early(void);
#else
void hudson_enable(device_t dev);
void __attribute__((weak)) hudson_setup_sata_phys(struct device *dev);
+void s3_resume_init_data(void *FchParams);
+
#endif
#endif /* HUDSON_H */
diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c
new file mode 100644
index 0000000000..0d40d6c8cc
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/resume.c
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "FchPlatform.h"
+#include "Fch.h"
+#include <cpu/amd/agesa/s3_resume.h>
+#include <device/device.h>
+#include "hudson.h"
+#include "AGESA.h"
+
+extern FCH_DATA_BLOCK InitEnvCfgDefault;
+extern FCH_INTERFACE FchInterfaceDefault;
+extern FCH_RESET_DATA_BLOCK InitResetCfgDefault;
+extern FCH_RESET_INTERFACE FchResetInterfaceDefault;
+
+#define DUMP_FCH_SETTING 0
+
+void s3_resume_init_data(void *data)
+{
+ FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)data;
+ AMD_CONFIG_PARAMS *StdHeader = FchParams->StdHeader;
+
+ *FchParams = InitEnvCfgDefault;
+ FchParams->StdHeader = StdHeader;
+
+ FchParams->Usb.Xhci0Enable = InitResetCfgDefault.FchReset.Xhci0Enable;
+ FchParams->Usb.Xhci1Enable = InitResetCfgDefault.FchReset.Xhci1Enable;
+ FchParams->Spi.SpiFastSpeed = InitResetCfgDefault.FastSpeed;
+ FchParams->Spi.WriteSpeed = InitResetCfgDefault.WriteSpeed;
+ FchParams->Spi.SpiMode = InitResetCfgDefault.Mode;
+ FchParams->Spi.AutoMode = InitResetCfgDefault.AutoMode;
+ FchParams->Spi.SpiBurstWrite = InitResetCfgDefault.BurstWrite;
+ FchParams->Sata.SataMode.Sata6AhciCap = (UINT8) InitResetCfgDefault.Sata6AhciCap;
+ FchParams->Misc.Cg2Pll = InitResetCfgDefault.Cg2Pll;
+ FchParams->Sata.SataMode.SataSetMaxGen2 = InitResetCfgDefault.SataSetMaxGen2;
+ FchParams->Sata.SataMode.SataClkMode = InitResetCfgDefault.SataClkMode;
+ FchParams->Sata.SataMode.SataModeReg = InitResetCfgDefault.SataModeReg;
+ FchParams->Sata.SataInternal100Spread = (UINT8) InitResetCfgDefault.SataInternal100Spread;
+ FchParams->Spi.SpiSpeed = InitResetCfgDefault.SpiSpeed;
+ FchParams->Gpp = InitResetCfgDefault.Gpp;
+ FchParams->Gpp.GppFunctionEnable = FchResetInterfaceDefault.GppEnable;
+
+ FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
+ FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present;
+ FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present;
+ FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present;
+ FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present;
+ FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
+ FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
+ FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
+ FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
+
+ FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
+ FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
+ FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
+ FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
+ FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
+ FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
+ FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
+ FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
+ FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
+ FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
+ FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
+ FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
+ FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid;
+ FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid;
+ FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid;
+ FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
+ FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid;
+ FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid;
+ FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress;
+ FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid;
+ FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid;
+ FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid;
+ FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid;
+ FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid;
+ FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid;
+ FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl;
+ FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl;
+
+ FchParams->Sd.SdConfig = FchInterfaceDefault.SdConfig;
+ FchParams->Azalia.AzaliaEnable = FchInterfaceDefault.AzaliaController;
+ FchParams->Ir.IrConfig = FchInterfaceDefault.IrConfig;
+ FchParams->Ab.NbSbGen2 = FchInterfaceDefault.UmiGen2;
+ FchParams->Sata.SataClass = FchInterfaceDefault.SataClass;
+ FchParams->Sata.SataMode.SataEnable = FchInterfaceDefault.SataEnable;
+ FchParams->Sata.SataMode.IdeEnable = FchInterfaceDefault.IdeEnable;
+ FchParams->Sata.SataIdeMode = FchInterfaceDefault.SataIdeMode;
+ FchParams->Usb.Ohci1Enable = FchInterfaceDefault.Ohci1Enable;
+ FchParams->Usb.Ehci1Enable = FchInterfaceDefault.Ohci1Enable;
+ FchParams->Usb.Ohci2Enable = FchInterfaceDefault.Ohci2Enable;
+ FchParams->Usb.Ehci2Enable = FchInterfaceDefault.Ohci2Enable;
+ FchParams->Usb.Ohci3Enable = FchInterfaceDefault.Ohci3Enable;
+ FchParams->Usb.Ehci3Enable = FchInterfaceDefault.Ohci3Enable;
+ FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable;
+ FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail;
+
+#if !CONFIG_HUDSON_XHCI_ENABLE
+ FchParams->Usb.Xhci0Enable = FALSE;
+#endif
+ FchParams->Usb.Xhci1Enable = FALSE;
+
+#if DUMP_FCH_SETTING
+ int i;
+
+ for (i = 0; i < sizeof(FchParams); i++) {
+ printk(BIOS_DEBUG, " %02x", ((u8 *) FchParams)[i]);
+ if ((i % 16) == 15)
+ printk(BIOS_DEBUG, "\n");
+ }
+#endif
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 23:08:43 +0000