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-rw-r--r--src/southbridge/amd/cs5536/chip.h1
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c9
2 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h
index 12cfecbd72..33cc78a2f1 100644
--- a/src/southbridge/amd/cs5536/chip.h
+++ b/src/southbridge/amd/cs5536/chip.h
@@ -9,6 +9,7 @@ struct southbridge_amd_cs5536_config {
int lpc_irq; /* what to enable, e.g. 0x18 */
int enable_gpio0_inta; /* almost always will be true */
int enable_ide_nand_flash; /* if you are using nand flash instead of IDE drive */
+ int enable_uarta; /* internal uarta interrupt enable */
};
#endif /* _SOUTHBRIDGE_AMD_CS5536 */
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index a2b3284cf5..062ba5a0f0 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -97,6 +97,15 @@ static void southbridge_enable(struct device *dev)
outl(0x3081, GPIOL_INPUT_INVERT_ENABLE);
outl(GPIOL_0_SET, GPIO_MAPPER_X);
}
+
+ if (sb->enable_uarta){
+ printk_err("%s: enable uarta, msr MDD_IRQM_YHIGH(%x) \n",
+ __FUNCTION__, MDD_IRQM_YHIGH);
+ msr = rdmsr(MDD_IRQM_YHIGH);
+ msr.lo |= 0x04000000;
+ wrmsr(MDD_IRQM_YHIGH, msr);
+ }
+
printk_err("%s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
if (sb->enable_ide_nand_flash) {
enable_ide_nand_flash();