diff options
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/early_setup.c | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/hudson.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5530/vga.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/early_setup.c | 14 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/early_setup.c | 4 |
5 files changed, 13 insertions, 13 deletions
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 8cf380bdf6..ed52108364 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -79,7 +79,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void) { u16 tmp = inw(PM1_CNT_BLK_ADDRESS); @@ -89,7 +89,7 @@ int acpi_get_sleep_type(void) } #endif -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int acpi_is_wakeup_early(void) { return (acpi_get_sleep_type() == 3); diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index ce450429fa..ce541fc0b5 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -30,7 +30,7 @@ #include "hudson.h" #include "smbus.h" -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void) { u16 tmp = inw(PM1_CNT_BLK_ADDRESS); diff --git a/src/southbridge/amd/cs5530/vga.c b/src/southbridge/amd/cs5530/vga.c index 56bea45ad5..66ab239efc 100644 --- a/src/southbridge/amd/cs5530/vga.c +++ b/src/southbridge/amd/cs5530/vga.c @@ -492,4 +492,4 @@ static const struct pci_driver vga_pci_driver __pci_driver = { .device = PCI_DEVICE_ID_CYRIX_5530_VIDEO, }; -#endif /* #if CONFIG_GX1_VIDEO == 1 */ +#endif /* #if CONFIG_GX1_VIDEO */ diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index 0540823f16..31b31736cd 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -147,7 +147,7 @@ static u8 is_famly10(void) return (cpuid_eax(1) & 0xff00000) != 0; } -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 static u8 l3_cache(void) { return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0; @@ -246,7 +246,7 @@ static void rs780_htinit(void) } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { printk(BIOS_INFO, "rs780_htinit: HT3 mode\n"); - #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ + #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 /* HT3 mode, RPR 8.4.3 */ set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0); @@ -282,11 +282,11 @@ static void rs780_htinit(void) /* Sets Training 0 Time. See T0Time table for encodings */ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20); /* TODO: */ - #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ + #endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ } } -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 /* save some spaces */ +#if !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 /******************************************************* * Optimize k8 with UMA. * See BKDG_NPT_0F guide for details. @@ -340,9 +340,9 @@ static void k8_optimization(void) } #else #define k8_optimization() do{}while(0) -#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */ +#endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 static void fam10_optimization(void) { device_t cpu_f0, cpu_f2, cpu_f3; @@ -405,7 +405,7 @@ static void fam10_optimization(void) } #else #define fam10_optimization() do{}while(0) -#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ +#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ /***************************************** * rs780_por_pcicfg_init() diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 0f54ba356c..c6131638ad 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -266,7 +266,7 @@ void sr5650_htinit(void) //set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26); /* HT Buffer Allocation for Ganged Links!!! */ -#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ +#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */ } } @@ -299,7 +299,7 @@ void fam10_optimization(void) } #else #define fam10_optimization() do{}while(0) -#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ +#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */ /***************************************** * Compliant with CIM_33's ATINB_PCICFG_POR_TABLE |