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-rw-r--r--src/southbridge/amd/rs780/cmn.c11
-rw-r--r--src/southbridge/amd/rs780/gfx.c3
-rw-r--r--src/southbridge/amd/rs780/rs780.h2
3 files changed, 10 insertions, 6 deletions
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index c39c6e9968..b849e1efa7 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -256,9 +256,6 @@ u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port)
u32 lc_state, reg, current_link_width, lane_mask;
int8_t current, res = 0;
u32 gfx_gpp_sb_sel;
- void set_pcie_dereset(void);
- void set_pcie_reset(void);
-
switch (port) {
case 2 ... 3:
gfx_gpp_sb_sel = PCIE_CORE_INDEX_GFX;
@@ -397,3 +394,11 @@ int is_family10h(void)
{
return cpuidFamily() == 0x10;
}
+
+__weak void set_pcie_reset(void)
+{
+}
+
+__weak void set_pcie_dereset(void)
+{
+}
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 3152a14eb1..cfcddb29f3 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -36,9 +36,6 @@
#include <cpu/x86/msr.h>
#include "rs780.h"
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
/* Trust the original resource allocation. Don't do it again. */
#undef DONT_TRUST_RESOURCE_ALLOCATION
//#define DONT_TRUST_RESOURCE_ALLOCATION
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index a8bbbe2231..ce46d96760 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -223,5 +223,7 @@ void enable_rs780_dev8(void);
void rs780_early_setup(void);
void rs780_htinit(void);
int is_dev3_present(void);
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
#endif /* __RS780_H__ */