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-rw-r--r--src/southbridge/amd/cs5535/Kconfig2
-rw-r--r--src/southbridge/amd/cs5535/Makefile.inc8
-rw-r--r--src/southbridge/amd/cs5535/chip.h8
-rw-r--r--src/southbridge/amd/cs5535/chipsetinit.c356
-rw-r--r--src/southbridge/amd/cs5535/cs5535.c111
-rw-r--r--src/southbridge/amd/cs5535/cs5535.h121
-rw-r--r--src/southbridge/amd/cs5535/early_setup.c145
-rw-r--r--src/southbridge/amd/cs5535/early_smbus.c22
-rw-r--r--src/southbridge/amd/cs5535/ide.c30
-rw-r--r--src/southbridge/amd/cs5535/smbus.h46
10 files changed, 0 insertions, 849 deletions
diff --git a/src/southbridge/amd/cs5535/Kconfig b/src/southbridge/amd/cs5535/Kconfig
deleted file mode 100644
index 8fcff288aa..0000000000
--- a/src/southbridge/amd/cs5535/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-config SOUTHBRIDGE_AMD_CS5535
- bool
diff --git a/src/southbridge/amd/cs5535/Makefile.inc b/src/southbridge/amd/cs5535/Makefile.inc
deleted file mode 100644
index 3785cd4002..0000000000
--- a/src/southbridge/amd/cs5535/Makefile.inc
+++ /dev/null
@@ -1,8 +0,0 @@
-ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5535),y)
-
-ramstage-y += cs5535.c
-#ramstage-y += pci.c
-#ramstage-y += ide.c
-ramstage-y += chipsetinit.c
-
-endif
diff --git a/src/southbridge/amd/cs5535/chip.h b/src/southbridge/amd/cs5535/chip.h
deleted file mode 100644
index 37e5eadddd..0000000000
--- a/src/southbridge/amd/cs5535/chip.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _SOUTHBRIDGE_AMD_CS5535
-#define _SOUTHBRIDGE_AMD_CS5535
-
-struct southbridge_amd_cs5535_config {
- int setupflash;
-};
-
-#endif /* _SOUTHBRIDGE_AMD_CS5535 */
diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c
deleted file mode 100644
index 1b7fe5dd80..0000000000
--- a/src/southbridge/amd/cs5535/chipsetinit.c
+++ /dev/null
@@ -1,356 +0,0 @@
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include "chip.h"
-#include "northbridge/amd/gx2/northbridge.h"
-#include <cpu/amd/gx2def.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/cache.h>
-#include "southbridge/amd/cs5535/cs5535.h"
-
-/* the structs in this file only set msr.lo. But ... that may not always be true */
-
-struct msrinit {
- unsigned long msrnum;
- msr_t msr;
-};
-
-/* Master Configuration Register for Bus Masters. */
-static struct msrinit SB_MASTER_CONF_TABLE[] = {
- { USB1_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, /* NOTE: Must be 1st entry in table */
- { USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} },
- { ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000} },
- { AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} },
- { MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000} },
-/* GLPCI_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/
-/* GLCP_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/
-/* GLIU_SB_GLD_MSR_CONF, 0x0*/
- {0,{0,0}}
-};
-
-/* 5535_A3 Clock Gating*/
-static struct msrinit CS5535_CLOCK_GATING_TABLE[] = {
- { USB1_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },
- { USB2_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },
- { GLIU_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} },
- { GLPCI_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },
- { GLCP_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} },
- { MDD_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x050554111} },
- { ATA_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },
- { AC97_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },
- { 0, {.hi = 0, .lo = 0x000000000} }
-};
-
-#ifdef UNUSED_CODE
-struct acpiinit {
- unsigned short ioreg;
- unsigned long regdata;
- unsigned short iolen;
-};
-
-static struct acpiinit acpi_init_table[] = {
- {ACPI_BASE+0x00, 0x01000000, 4},
- {ACPI_BASE+0x08, 0, 4},
- {ACPI_BASE+0x0C, 0, 4},
- {ACPI_BASE+0x1C, 0, 4},
- {ACPI_BASE+0x18, 0x0FFFFFFFF, 4},
- {ACPI_BASE+0x00, 0x0000FFFF, 4},
-
- {PM_SCLK, 0x000000E00, 4},
- {PM_SED, 0x000004601, 4},
- {PM_SIDD, 0x000008C02, 4},
- {PM_WKD, 0x0000000A0, 4},
- {PM_WKXD, 0x0000000A0, 4},
- {0,0,0}
-};
-
-/*****************************************************************************
- *
- * pmChipsetInit
- *
- * Program ACPI LBAR and initialize ACPI registers.
- *
- *****************************************************************************/
-static void pmChipsetInit(void)
-{
- unsigned long val = 0;
- unsigned short port;
-
- port = (PMLogic_BASE + 0x010);
- val = 0x0E00 ; /* 1ms*/
- outl(val, port);
-
- /* PM_WKXD*/
- /* Make sure bits[3:0]=0000b to clear the*/
- /* saved Sx state*/
- port = (PMLogic_BASE + 0x034);
- val = 0x0A0 ; /* 5ms*/
- outl(val, port);
-
- /* PM_WKD*/
- port = (PMLogic_BASE + 0x030);
- outl(val, port);
-
- /* PM_SED*/
- port = (PMLogic_BASE + 0x014);
- val = 0x04601 ; /* 5ms*/
- outl(val, port);
-
- /* PM_SIDD*/
- port = (PMLogic_BASE + 0x020);
- val = 0x08C02 ; /* 10ms*/
- outl(val, port);
-
- /* GPIO24 OUT_AUX1 function is the external signal for 5535's
- * vsb_working_aux which is de-asserted when 5535 enters Standby (S3 or
- * S5) state. On Hawk, GPIO24 controls all voltage rails except Vmem
- * and Vstandby. This means GX2 will be fully de-powered if this
- * control de-asserts in S3/S5.
- */
-
- /* GPIO24 is setup in preChipsetInit for two reasons
- * 1. GPIO24 at reset defaults to disabled, since this signal is
- * vsb_work_aux on Hawk it controls the FET's for all voltage
- * rails except Vstandby & Vmem. BIOS needs to enable GPIO24 as
- * OUT_AUX1 & OUTPUT_EN early so it is driven by 5535.
- * 2. Non-PM builds will require GPIO24 enabled for instant-off power
- * button
- */
-
- /* GPIO11 OUT_AUX1 function is the external signal for 5535's
- * slp_clk_n which is asserted when 5535 enters Sleep(S1) state.
- * On Hawk, GPIO11 is connected to control input of external clock
- * generator for 14MHz, PCI, USB & LPC clocks.
- * Programming of GPIO11 will be done by VSA PM code. During VSA
- * Init. BIOS writes PM Core Virtual Register indicating if S1 Clocks
- * should be On or Off. This is based on a Setup item. We do not want
- * to leave GPIO11 enabled because of a Hawk board problem. With
- * GPIO11 enabled in S3, something is back-driving GPIO11 causing it
- * to float to 1.6-1.7V.
- */
-}
-#endif
-
-struct FLASH_DEVICE {
- unsigned char fType; /* Flash type: NOR or NAND */
- unsigned char fInterface; /* Flash interface: I/O or Memory */
- unsigned long fMask; /* Flash size/mask */
-};
-
-static struct FLASH_DEVICE FlashInitTable[] = {
- { FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K }, /* CS0, or Flash Device 0 */
- { FLASH_TYPE_NONE, 0, 0 }, /* CS1, or Flash Device 1 */
- { FLASH_TYPE_NONE, 0, 0 }, /* CS2, or Flash Device 2 */
- { FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */
-};
-
-#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
-
-static uint32_t FlashPort[] = {
- MDD_LBAR_FLSH0,
- MDD_LBAR_FLSH1,
- MDD_LBAR_FLSH2,
- MDD_LBAR_FLSH3
-};
-
-/***************************************************************************
- *
- * ChipsetFlashSetup
- *
- * Flash LBARs need to be setup before VSA init so the PCI BARs have
- * correct size info. Call this routine only if flash needs to be
- * configured (don't call it if you want IDE).
- *
- **************************************************************************/
-static void ChipsetFlashSetup(void)
-{
- msr_t msr;
- int i;
- int numEnabled = 0;
-
- printk(BIOS_DEBUG, "ChipsetFlashSetup++\n");
- for (i = 0; i < FlashInitTableLen; i++) {
- if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
- printk(BIOS_DEBUG, "Enable CS%d\n", i);
- /* we need to configure the memory/IO mask */
- msr = rdmsr(FlashPort[i]);
- msr.hi = 0; /* start with the "enabled" bit clear */
- if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
- msr.hi |= 0x00000002;
- else
- msr.hi &= ~0x00000002;
- if (FlashInitTable[i].fInterface == FLASH_IF_MEM)
- msr.hi |= 0x00000004;
- else
- msr.hi &= ~0x00000004;
- msr.hi |= FlashInitTable[i].fMask;
- printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
- wrmsr(FlashPort[i], msr);
-
- /* now write-enable the device */
- msr = rdmsr(MDD_NORF_CNTRL);
- msr.lo |= (1 << i);
- printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
- wrmsr(MDD_NORF_CNTRL, msr);
-
- /* update the number enabled */
- numEnabled++;
- }
- }
-
- /* enable the flash */
- if (0 != numEnabled) {
- msr = rdmsr(MDD_PIN_OPT);
- msr.lo &= ~1; /* PIN_OPT_IDE */
- printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
- wrmsr(MDD_PIN_OPT, msr);
- }
-
- printk(BIOS_DEBUG, "ChipsetFlashSetup--\n");
-}
-
-
-
-/****************************************************************************
- *
- * ChipsetGeodeLinkInit
- *
- * Handle chipset specific GeodeLink settings here.
- * Called from GeodeLink init code.
- *
- ****************************************************************************/
-static void
-ChipsetGeodeLinkInit(void)
-{
- msr_t msr;
- unsigned long msrnum;
- unsigned long totalmem;
-
- /* SWASIF for A1 DMA */
- /* Set all memory to "just above systop" PCI so DMA will work */
-
- /* check A1 */
- msrnum = MSR_SB_GLCP + 0x17;
- msr = rdmsr(msrnum);
- if ((msr.lo&0xff) == 0x11)
- return;
-
- totalmem = (sizeram() << 20) - 1; // highest address
- totalmem >>= 12;
- totalmem = ~totalmem;
- totalmem &= 0xfffff;
- msr.lo = totalmem;
- msr.hi = 0x20000000; /* Port 1 (PCI) */
- msrnum = MSR_SB_GLIU + 0x20;
- wrmsr(msrnum, msr);
-}
-
-void
-chipsetinit(void)
-{
- device_t dev;
- struct southbridge_amd_cs5535_config *sb;
- msr_t msr;
- struct msrinit *csi;
- int i;
- unsigned long msrnum;
-
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_NS_CS5535_ISA, 0);
-
- if (!dev) {
- printk(BIOS_ERR, "CS5535 not found.\n");
- return;
- }
-
- sb = (struct southbridge_amd_cs5535_config *)dev->chip_info;
-
- if (!sb) {
- printk(BIOS_ERR, "CS5535 configuration not found.\n");
- return;
- }
-
- post_code(P80_CHIPSET_INIT);
- ChipsetGeodeLinkInit();
-
-#ifdef UNUSED_CODE
- /* we hope NEVER to be in coreboot when S3 resumes
- if (! IsS3Resume()) */
- {
- struct acpiinit *aci = acpi_init_table;
- while (aci->ioreg){
- if (aci->iolen == 2) {
- outw(aci->regdata, aci->ioreg);
- inw(aci->ioreg);
- } else {
- outl(aci->regdata, aci->ioreg);
- inl(aci->ioreg);
- }
- }
-
- pmChipsetInit();
- }
-#endif
-
- /* Setup USB. Need more details. #118.18 */
- msrnum = MSR_SB_USB1 + 8;
- msr.lo = 0x00012090;
- msr.hi = 0;
- wrmsr(msrnum, msr);
- msrnum = MSR_SB_USB2 + 8;
- wrmsr(msrnum, msr);
-
- /* set hd IRQ */
- outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE);
- outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT);
-
- /* Allow IO read and writes during a ATA DMA operation. */
- /* This could be done in the HD ROM but do it here for easier debugging. */
-
- msrnum = ATA_SB_GLD_MSR_ERR;
- msr = rdmsr(msrnum);
- msr.lo &= ~0x100;
- wrmsr(msrnum, msr);
-
- /* Enable Post Primary IDE. */
- msrnum = GLPCI_SB_CTRL;
- msr = rdmsr(msrnum);
- msr.lo |= GLPCI_CRTL_PPIDE_SET;
- wrmsr(msrnum, msr);
-
- /* Set up Master Configuration Register */
- /* If 5536, use same master config settings as 5535, except for OHCI MSRs */
- i = 0;
-
- csi = &SB_MASTER_CONF_TABLE[i];
- for (; csi->msrnum; csi++){
- msr.lo = csi->msr.lo;
- msr.hi = csi->msr.hi;
- wrmsr(csi->msrnum, msr); // MSR - see table above
- }
-
- /* Flash Setup */
- printk(BIOS_INFO, "%sDOING ChipsetFlashSetup()!\n",
- sb->setupflash ? "" : "NOT ");
-
- if (sb->setupflash)
- ChipsetFlashSetup();
-
- /* Set up Hardware Clock Gating */
-
- /* if (getnvram(TOKEN_SB_CLK_GATE) != TVALUE_DISABLE) */
- {
- csi = CS5535_CLOCK_GATING_TABLE;
-
- for (; csi->msrnum; csi++){
- msr.lo = csi->msr.lo;
- msr.hi = csi->msr.hi;
- wrmsr(csi->msrnum, msr); // MSR - see table above
- }
- }
-}
diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c
deleted file mode 100644
index 67d7eee334..0000000000
--- a/src/southbridge/amd/cs5535/cs5535.c
+++ /dev/null
@@ -1,111 +0,0 @@
-
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "cs5535.h"
-
-static void nvram_on(struct device *dev)
-{
-#if 0
- volatile char *flash = (volatile unsigned char *)0xFFFc0000;
- unsigned char id1, id2;
-#endif
- unsigned char reg;
-
- /* Enable writes to flash at top of memory */
- pci_write_config8(dev, 0x52, 0xee);
-
- /* Set positive decode on ROM */
- /* Also, there is no apparent reason to turn off the device on the */
- /* IDE devices */
-
- reg = pci_read_config8(dev, 0x5b);
- reg |= 1 << 5; /* ROM Decode */
- reg |= 1 << 3; /* Primary IDE decode */
- reg |= 1 << 4; /* Secondary IDE decode */
-
- pci_write_config8(dev, 0x5b, reg);
-
-#if 0 // just to test if the flash is accessible!
- *(flash + 0x555) = 0xaa;
- *(flash + 0x2aa) = 0x55;
- *(flash + 0x555) = 0x90;
-
- id1 = *(volatile unsigned char *) flash;
- id2 = *(volatile unsigned char *) (flash + 1);
-
- *flash = 0xf0;
-
- printk(BIOS_DEBUG, "Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
-#endif
-}
-
-
-static void southbridge_init(struct device *dev)
-{
- printk(BIOS_SPEW, "cs5535: %s\n", __func__);
- nvram_on(dev);
-}
-
-/*
-static void dump_south(struct device *dev)
-{
- int i, j;
-
- for (i = 0; i < 256; i+=16) {
- printk(BIOS_DEBUG, "0x%02x:", i);
- for (j = 0; j < 16; j++)
- printk(BIOS_DEBUG, " %02x", pci_read_config8(dev, i+j));
- printk(BIOS_DEBUG, "\n");
- }
-}
-*/
-
-static void southbridge_enable(struct device *dev)
-{
- printk(BIOS_SPEW, "%s: dev is %p\n", __func__, dev);
-}
-
-static void cs5535_read_resources(device_t dev)
-{
- struct resource *res;
-
- pci_dev_read_resources(dev);
-
- res = new_resource(dev, 1);
- res->base = 0x0UL;
- res->size = 0x1000UL;
- res->limit = 0xffffUL;
- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = IO_APIC_ADDR;
- res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static struct device_operations southbridge_ops = {
- .read_resources = cs5535_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = southbridge_init,
- .enable = southbridge_enable,
-};
-
-static const struct pci_driver cs5535_pci_driver __pci_driver = {
- .ops = &southbridge_ops,
- .vendor = PCI_VENDOR_ID_NS,
- .device = PCI_DEVICE_ID_NS_CS5535
-};
-
-struct chip_operations southbridge_amd_cs5535_ops = {
- CHIP_NAME("AMD Geode CS5535 Southbridge")
- /* This is only called when this device is listed in the
- * static device tree.
- */
- .enable_dev = southbridge_enable,
-};
diff --git a/src/southbridge/amd/cs5535/cs5535.h b/src/southbridge/amd/cs5535/cs5535.h
deleted file mode 100644
index 2bb9a6e7b5..0000000000
--- a/src/southbridge/amd/cs5535/cs5535.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Nils Jacobs
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _CS5535_H
-#define _CS5535_H
-
-/* SouthBridge Equates */
-#define CS5535_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */
-#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */
-#define MSR_SB ((CS5535_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */
-#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
-
-#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */
-#define SMBUS_IO_BASE 0x6000
-#define GPIO_IO_BASE 0x6100
-#define MFGPT_IO_BASE 0x6200
-#define ACPI_IO_BASE 0x9C00
-#define PMS_IO_BASE 0x9D00
-
-/* Cs5536 as follows. */
-/* SB_GLIU */
-/* port0 - GLIU */
-/* port1 - GLPCI */
-/* port2 - USB Controller #2 */
-/* port3 - ATA-5 Controller */
-/* port4 - MDD */
-/* port5 - AC97 */
-/* port6 - USB Controller #1 */
-/* port7 - GLCP */
-
-#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
-#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
-#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */
-#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */
-#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
-#define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */
-#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */
-#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */
-
-/* GLIU */
-#define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04)
-
-/* USB1 */
-#define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01)
-#define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04)
-
-/* USB2 */
-#define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01)
-#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04)
-
-/* ATA */
-#define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01)
-#define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03)
-#define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04)
-#define ATA_SB_IDE_CFG (MSR_SB_ATA + 0x10)
-
-/* AC97 */
-#define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01)
-#define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04)
-
-/* GLPCI */
-#define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04)
-#define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10)
-#define GLPCI_CRTL_PPIDE_SET (1 << 17)
-
-/* GLCP */
-#define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04)
-
-/* MDD */
-#define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01)
-#define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04)
-#define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B)
-#define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C)
-#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D)
-#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E)
-#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F)
-#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x10)
-#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x11)
-#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x12)
-#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x13)
-#define MDD_PIN_OPT (MSR_SB_MDD + 0x15)
-#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x18)
-
-/* GPIO */
-#define GPIOL_2_SET (1 << 2)
-
-/* GPIO LOW Bank Bit Registers */
-#define GPIOL_INPUT_ENABLE (0x20)
-#define GPIOL_IN_AUX1_SELECT (0x34)
-
-/* FLASH device macros */
-#define FLASH_TYPE_NONE 0 /* No flash device installed */
-#define FLASH_TYPE_NAND 1 /* NAND device */
-
-#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */
-
-/* Flash Memory Mask values */
-#define FLASH_MEM_4K 0xFFFFF000
-
-#if !defined(__ASSEMBLER__)
-#if defined(__PRE_RAM__)
-void cs5535_disable_internal_uart(void);
-#else
-void chipsetinit(void);
-#endif
-#endif
-
-#endif /* _CS5535_H */
diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c
deleted file mode 100644
index 1030aa0e88..0000000000
--- a/src/southbridge/amd/cs5535/early_setup.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- *
- * cs5535_early_setup.c: Early chipset initialization for CS5535 companion device
- *
- *
- * This file implements the initialization sequence documented in section 4.2 of
- * AMD Geode GX Processor CS5535 Companion Device GoedeROM Porting Guide.
- *
- */
-
-/**
- * @brief Setup PCI IDSEL for CS5535
- *
- *
- */
-
-static void cs5535_setup_extmsr(void)
-{
- msr_t msr;
-
- /* forward MSR access to CS5535_GLINK_PORT_NUM to CS5535_DEV_NUM */
- msr.hi = msr.lo = 0x00000000;
-#if CS5535_GLINK_PORT_NUM <= 4
- msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8);
-#else
- msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8);
-#endif
- wrmsr(0x5000201e, msr);
-}
-
-static void cs5535_setup_idsel(void)
-{
- /* write IDSEL to the write once register at address 0x0000 */
- outl(0x1 << (CS5535_DEV_NUM + 10), 0);
-}
-
-static void cs5535_usb_swapsif(void)
-{
- msr_t msr;
-
- msr = rdmsr(0x51600005);
- //USB Serial short detect bit.
- if (msr.hi & 0x10) {
- /* We need to preserve bits 32,33,35 and not clear any BIST error, but clear the
- * SERSHRT error bit */
- msr.hi &= 0xFFFFFFFB;
- wrmsr(0x51600005, msr);
- }
-}
-
-static void cs5535_setup_iobase(void)
-{
- msr_t msr;
- /* setup LBAR for SMBus controller */
- msr.hi = 0x0000f001;
- msr.lo = SMBUS_IO_BASE;
- wrmsr(MDD_LBAR_SMB, msr);
-
- /* setup LBAR for GPIO */
- msr.hi = 0x0000f001;
- msr.lo = GPIO_IO_BASE;
- wrmsr(MDD_LBAR_GPIO, msr);
-
- /* setup LBAR for MFGPT */
- msr.hi = 0x0000f001;
- msr.lo = MFGPT_IO_BASE;
- wrmsr(MDD_LBAR_MFGPT, msr);
-
- /* setup LBAR for ACPI */
- msr.hi = 0x0000f001;
- msr.lo = ACPI_IO_BASE;
- wrmsr(MDD_LBAR_ACPI, msr);
-
- /* setup LBAR for PM Support */
- msr.hi = 0x0000f001;
- msr.lo = PMS_IO_BASE;
- wrmsr(MDD_LBAR_PMS, msr);
-}
-
-static void cs5535_setup_gpio(void)
-{
- uint32_t val;
-
- /* setup GPIO pins 14/15 for SDA/SCL */
- val = (1<<14 | 1<<15);
- /* Output Enable */
- outl(0x3fffc000, 0x6100 + 0x04);
- //outl(val, 0x6100 + 0x04);
- /* Output AUX1 */
- outl(0x3fffc000, 0x6100 + 0x10);
- //outl(val, 0x6100 + 0x10);
- /* Input Enable */
- //outl(0x0f5af0a5, 0x6100 + 0x20);
- outl(0x3fffc000, 0x6100 + 0x20);
- //outl(val, 0x6100 + 0x20);
- /* Input AUX1 */
- //outl(0x3ffbc004, 0x6100 + 0x34);
- outl(0x3fffc000, 0x6100 + 0x34);
- //outl(val, 0x6100 + 0x34);
-}
-
-void cs5535_disable_internal_uart(void)
-{
-}
-
-static void cs5535_setup_cis_mode(void)
-{
- msr_t msr;
-
- /* Setup CPU serial SouthBridge interface to mode C. */
- msr = rdmsr(GLPCI_SB_CTRL);
- msr.lo &= ~0x18;
- msr.lo |= 0x10;
- wrmsr(GLPCI_SB_CTRL, msr);
-}
-
-static void dummy(void)
-{
-}
-
-static void cs5535_early_setup(void)
-{
- msr_t msr;
-
- cs5535_setup_extmsr();
-
- msr = rdmsr(GLCP_SYS_RSTPLL);
- if (msr.lo & (0x3f << 26)) {
- /* PLL is already set and we are reboot from PLL reset */
- printk(BIOS_DEBUG, "reboot from BIOS reset\n");
- return;
- }
- printk(BIOS_DEBUG, "Setup idsel\n");
- cs5535_setup_idsel();
- printk(BIOS_DEBUG, "Setup iobase\n");
- cs5535_usb_swapsif();
- cs5535_setup_iobase();
- printk(BIOS_DEBUG, "Setup gpio\n");
- cs5535_setup_gpio();
- printk(BIOS_DEBUG, "Setup cis_mode\n");
- cs5535_setup_cis_mode();
- printk(BIOS_DEBUG, "Setup smbus\n");
- cs5535_enable_smbus();
- dummy();
-}
diff --git a/src/southbridge/amd/cs5535/early_smbus.c b/src/southbridge/amd/cs5535/early_smbus.c
deleted file mode 100644
index 25b6951daa..0000000000
--- a/src/southbridge/amd/cs5535/early_smbus.c
+++ /dev/null
@@ -1,22 +0,0 @@
-#include "smbus.h"
-
-#define SMBUS_IO_BASE 0x6000
-
-/* initialization for SMBus Controller */
-static void cs5535_enable_smbus(void)
-{
- unsigned char val;
-
- /* reset SMBUS controller */
- outb(0, SMBUS_IO_BASE + SMB_CTRL2);
-
- /* Set SCL freq and enable SMB controller */
- val = inb(SMBUS_IO_BASE + SMB_CTRL2);
- val |= ((0x20 << 1) | SMB_CTRL2_ENABLE);
- outb(val, SMBUS_IO_BASE + SMB_CTRL2);
-
- /* Setup SMBus host controller address to 0xEF */
- val = inb(SMBUS_IO_BASE + SMB_ADD);
- val |= (0xEF | SMB_ADD_SAEN);
- outb(val, SMBUS_IO_BASE + SMB_ADD);
-}
diff --git a/src/southbridge/amd/cs5535/ide.c b/src/southbridge/amd/cs5535/ide.c
deleted file mode 100644
index b997ca2463..0000000000
--- a/src/southbridge/amd/cs5535/ide.c
+++ /dev/null
@@ -1,30 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "cs5535.h"
-
-static void ide_init(struct device *dev)
-{
- printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);
-}
-
-static void ide_enable(struct device *dev)
-{
- printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);
-}
-
-static struct device_operations ide_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = ide_init,
- .enable = ide_enable,
-};
-
-static const struct pci_driver ide_driver __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_NS,
- .device = PCI_DEVICE_ID_NS_CS5535_IDE,
-};
diff --git a/src/southbridge/amd/cs5535/smbus.h b/src/southbridge/amd/cs5535/smbus.h
deleted file mode 100644
index db35f6ee7b..0000000000
--- a/src/southbridge/amd/cs5535/smbus.h
+++ /dev/null
@@ -1,46 +0,0 @@
-//#include <device/smbus_def.h>
-#define SMBUS_ERROR -1
-#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
-#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
-
-#define SMB_SDA 0x00
-#define SMB_STS 0x01
-#define SMB_CTRL_STS 0x02
-#define SMB_CTRL1 0x03
-#define SMB_ADD 0x04
-#define SMB_CTRL2 0x05
-#define SMB_CTRL3 0x06
-
-#define SMB_STS_SLVSTP (0x01 << 7)
-#define SMB_STS_SDAST (0x01 << 6)
-#define SMB_STS_BER (0x01 << 5)
-#define SMB_STS_NEGACK (0x01 << 4)
-#define SMB_STS_STASTR (0x01 << 3)
-#define SMB_STS_NMATCH (0x01 << 2)
-#define SMB_STS_MASTER (0x01 << 1)
-#define SMB_STS_XMIT (0x01 << 0)
-
-#define SMB_CSTS_TGSCL (0x01 << 5)
-#define SMB_CSTS_TSDA (0x01 << 4)
-#define SMB_CSTS_GCMTCH (0x01 << 3)
-#define SMB_CSTS_MATCH (0x01 << 2)
-#define SMB_CSTS_BB (0x01 << 1)
-#define SMB_CSTS_BUSY (0x01 << 0)
-
-#define SMB_CTRL1_STASTRE (0x01 << 7)
-#define SMB_CTRL1_NMINTE (0x01 << 6)
-#define SMB_CTRL1_GCMEN (0x01 << 5)
-#define SMB_CTRL1_ACK (0x01 << 4)
-#define SMB_CTRL1_RSVD (0x01 << 3)
-#define SMB_CTRL1_INTEN (0x01 << 2)
-#define SMB_CTRL1_STOP (0x01 << 1)
-#define SMB_CTRL1_START (0x01 << 0)
-
-#define SMB_ADD_SAEN (0x01 << 7)
-
-#define SMB_CTRL2_ENABLE 0x01
-
-#define SMBUS_TIMEOUT (100*1000*10)
-#define SMBUS_STATUS_MASK 0xfbff
-
-#define SMBUS_IO_BASE 0x6000
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 10:44:36 +0000