diff options
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/cs5535/cs5535_early_smbus.c | 44 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5535/cs5535_smbus.h | 90 |
2 files changed, 73 insertions, 61 deletions
diff --git a/src/southbridge/amd/cs5535/cs5535_early_smbus.c b/src/southbridge/amd/cs5535/cs5535_early_smbus.c index 4a57dd7438..b7dd436887 100644 --- a/src/southbridge/amd/cs5535/cs5535_early_smbus.c +++ b/src/southbridge/amd/cs5535/cs5535_early_smbus.c @@ -3,35 +3,39 @@ #define SMBUS_IO_BASE 0x6000 /* initialization for SMBus Controller */ -static int enable_smbus(void) +static int cs5535_enable_smbus(void) { unsigned char val; - /* FixME: move to early_iobase.c */ - /* setup LBAR for SMBus controller */ - __builtin_wrmsr(0x5140000B, 0x00006000, 0x0000f001); - /* setup LBAR for GPIO at 0x6100 */ - __builtin_wrmsr(0x5140000C, 0x00006100, 0x0000f001); - - - /* setup GPIO pins for SDA/SCL */ - - /* Setup SMBus host controller address to 0xEF */ - val = inb(SMBUS_IO_BASE + SMB_ADD); - val |= (0xEF | SMB_ADD_SAEN); - outb(val, SMBUS_IO_BASE + SMB_ADD); + outb(0, SMBUS_IO_BASE + SMB_CTRL2); /* Set SCL freq and enable SMB controller */ - outb(0x00, SMBUS_IO_BASE + SMB_CTRL2); val = inb(SMBUS_IO_BASE + SMB_CTRL2); - val |= (0x7F < 1) | SMB_CTRL2_ENABLE; + val |= ((0x7F << 1) | SMB_CTRL2_ENABLE); outb(val, SMBUS_IO_BASE + SMB_CTRL2); - /* Is SDA pulled high ? */ - val = inb(SMBUS_IO_BASE + SMB_CTRL_STS); - if (val & SMB_CSTS_TSDA) - return SMBUS_ERROR; + /* Setup SMBus host controller address to 0xEF */ + val = inb(SMBUS_IO_BASE + SMB_ADD); + val |= (0xEF | SMB_ADD_SAEN); + outb(val, SMBUS_IO_BASE + SMB_ADD); +#if 0 + print_debug("SMBUS registers "); + print_debug_hex8(inb(SMBUS_IO_BASE)); + print_debug(" "); + print_debug_hex8(inb(SMBUS_IO_BASE + 1)); + print_debug(" "); + print_debug_hex8(inb(SMBUS_IO_BASE + 2)); + print_debug(" "); + print_debug_hex8(inb(SMBUS_IO_BASE + 3)); + print_debug(" "); + print_debug_hex8(inb(SMBUS_IO_BASE + 4)); + print_debug(" "); + print_debug_hex8(inb(SMBUS_IO_BASE + 5)); + print_debug(" "); + print_debug_hex8(inb(SMBUS_IO_BASE + 6)); + print_debug("\n\r"); +#endif } #if 0 diff --git a/src/southbridge/amd/cs5535/cs5535_smbus.h b/src/southbridge/amd/cs5535/cs5535_smbus.h index 3a2e4928bf..2504f5dbef 100644 --- a/src/southbridge/amd/cs5535/cs5535_smbus.h +++ b/src/southbridge/amd/cs5535/cs5535_smbus.h @@ -3,46 +3,49 @@ #define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2 #define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3 -enum smb_native_registers { - SMB_SDA = 0x00, SMB_STS = 0x01, SMB_CTRL_STS = 0x02, - SMB_CTRL1 = 0x03, SMB_ADD = 0x04, SMB_CTRL2 = 0x05, - SMB_CTRL3 = 0x06 -}; - -enum smb_sts_bits { - SMB_STS_SLVSTP = (0x01 << 7), SMB_STS_SDAST = (0x01 << 6), - SMB_STS_BER = (0x01 << 5), SMB_STS_NEGACK = (0x01 << 4), - SMB_STS_STASTR = (0x01 << 3), SMB_STS_NMATCH = (0x01 << 2), - SMB_STS_MASTER = (0x01 << 1), SMB_STS_XMIT = (0x01 << 0) -}; - -enum smb_ctrl_sts_bits { - SMB_CSTS_TGSCL = (0x01 << 5), SMB_CSTS_TSDA = (0x01 << 4), - SMB_CSTS_GCMTCH = (0x01 << 3), SMB_CSTS_MATCH = (0x01 << 2), - SMB_CSTS_BB = (0x01 << 1), SMB_CSTS_BUSY = (0x01 << 0) -}; - -enum smb_ctrl1_bits { - SMB_CTRL1_STASTRE = (0x01 << 7), SMB_CTRL1_NMINTE = (0x01 << 6), - SMB_CTRL1_GCMEN = (0x01 << 5), SMB_CTRL1_ACK = (0x01 << 4), - SMB_CTRL1_RSVD = (0x01 << 3), SMB_CTRL1_INTEN = (0x01 << 2), - SMB_CTRL1_STOP = (0x01 << 1), SMB_CTRL1_START = (0x01 << 0) -}; - -enum smb_add_bits { - SMB_ADD_SAEN = (0x01 << 7) -}; - -enum smb_ctrl2_bits { - SMB_CTRL2_ENABLE = 0x01, -}; +#define SMB_SDA 0x00 +#define SMB_STS 0x01 +#define SMB_CTRL_STS 0x02 +#define SMB_CTRL1 0x03 +#define SMB_ADD 0x04 +#define SMB_CTRL2 0x05 +#define SMB_CTRL3 0x06 + +#define SMB_STS_SLVSTP (0x01 << 7) +#define SMB_STS_SDAST (0x01 << 6) +#define SMB_STS_BER (0x01 << 5) +#define SMB_STS_NEGACK (0x01 << 4) +#define SMB_STS_STASTR (0x01 << 3) +#define SMB_STS_NMATCH (0x01 << 2) +#define SMB_STS_MASTER (0x01 << 1) +#define SMB_STS_XMIT (0x01 << 0) + +#define SMB_CSTS_TGSCL (0x01 << 5) +#define SMB_CSTS_TSDA (0x01 << 4) +#define SMB_CSTS_GCMTCH (0x01 << 3) +#define SMB_CSTS_MATCH (0x01 << 2) +#define SMB_CSTS_BB (0x01 << 1) +#define SMB_CSTS_BUSY (0x01 << 0) + +#define SMB_CTRL1_STASTRE (0x01 << 7) +#define SMB_CTRL1_NMINTE (0x01 << 6) +#define SMB_CTRL1_GCMEN (0x01 << 5) +#define SMB_CTRL1_ACK (0x01 << 4) +#define SMB_CTRL1_RSVD (0x01 << 3) +#define SMB_CTRL1_INTEN (0x01 << 2) +#define SMB_CTRL1_STOP (0x01 << 1) +#define SMB_CTRL1_START (0x01 << 0) + +#define SMB_ADD_SAEN (0x01 << 7) + +#define SMB_CTRL2_ENABLE 0x01 #define SMBUS_TIMEOUT (100*1000*10) #define SMBUS_STATUS_MASK 0xfbff -static inline void smbus_delay(void) +static void smbus_delay(void) { - outb(0x80, 0x80); + outb(0x80, 0x80); } /* generate a smbus start condition */ @@ -124,19 +127,24 @@ static int smbus_send_command(unsigned smbus_io_base, unsigned char command) return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; } -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address) +static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address) { unsigned char val; - smbus_start_condition(smbus_io_base); + if (smbus_start_condition(smbus_io_base) < 0) + print_debug("smbus error 1"); - smbus_send_slave_address(smbus_io_base, device); + if (smbus_send_slave_address(smbus_io_base, device) < 0) + print_debug("smbus error 2"); - smbus_send_command(smbus_io_base, address); + if (smbus_send_command(smbus_io_base, address) < 0) + print_debug("smbus error 3"); - smbus_start_condition(smbus_io_base); + if (smbus_start_condition(smbus_io_base) < 0) + print_debug("smbus error 4"); - smbus_send_slave_address(smbus_io_base, device | 0x01); + if (smbus_send_slave_address(smbus_io_base, device | 0x01)) + print_debug("smbus error 5"); val = inb(smbus_io_base + SMB_CTRL1); outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1); |