4 files changed, 22 insertions, 33 deletions

diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index 91ebe036a9..4f769fb1a5 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -15,24 +15,22 @@
 
 config SOUTHBRIDGE_AMD_AGESA_BOLTON
 	bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET
 
 config SOUTHBRIDGE_AMD_AGESA_HUDSON
 	bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET
 
 config SOUTHBRIDGE_AMD_AGESA_YANGTZE
 	bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET
 
 if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
 
+config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select IOAPIC
+	select HAVE_USBDEBUG_OPTIONS
+	select HAVE_CF9_RESET
+	select HAVE_CF9_RESET_PREPARE
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/amd/agesa/hudson/bootblock.c"
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
index 315456dbd6..83eaa46bb4 100644
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ b/src/southbridge/amd/agesa/hudson/reset.c
@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <cf9_reset.h>
 #include <reset.h>
 
 #define HT_INIT_CONTROL     0x6c
@@ -24,7 +25,7 @@
 #define HTIC_BIOSR_Detect  (1<<5)
 #define HTIC_INIT_Detect   (1<<6)
 
-static void set_bios_reset(void)
+void cf9_reset_prepare(void)
 {
 	u32 htic;
 	htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
@@ -32,11 +33,7 @@ static void set_bios_reset(void)
 	pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
 }
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
-	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
-	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+	system_reset();
 }
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index 5ac876f6c4..9d803beea3 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -15,27 +15,25 @@
 
 config SOUTHBRIDGE_AMD_PI_BOLTON
 	bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET
 
 config SOUTHBRIDGE_AMD_PI_AVALON
 	bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET
 
 config SOUTHBRIDGE_AMD_PI_KERN
 	bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET
 
 config HUDSON_DISABLE_IMC
 	bool
 
 if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN
 
+config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select IOAPIC
+	select HAVE_USBDEBUG_OPTIONS
+	select HAVE_CF9_RESET
+	select HAVE_CF9_RESET_PREPARE
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/amd/pi/hudson/bootblock.c"
diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c
index f80e2d4c32..83eaa46bb4 100644
--- a/src/southbridge/amd/pi/hudson/reset.c
+++ b/src/southbridge/amd/pi/hudson/reset.c
@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <cf9_reset.h>
 #include <reset.h>
 
 #define HT_INIT_CONTROL     0x6c
@@ -24,7 +25,7 @@
 #define HTIC_BIOSR_Detect  (1<<5)
 #define HTIC_INIT_Detect   (1<<6)
 
-static void set_bios_reset(void)
+void cf9_reset_prepare(void)
 {
 	u32 htic;
 	htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
@@ -32,12 +33,7 @@ static void set_bios_reset(void)
 	pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
 }
 
-
-void do_hard_reset(void)
+void do_board_reset(void)
 {
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
-	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
-	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+	system_reset();
 }