summaryrefslogtreecommitdiff
path: root/src/southbridge/amd
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/sb700/early_setup.c79
-rw-r--r--src/southbridge/amd/sb700/fadt.c27
-rw-r--r--src/southbridge/amd/sb700/lpc.c22
-rw-r--r--src/southbridge/amd/sb700/sb700.h5
4 files changed, 106 insertions, 27 deletions
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index f1f0548a79..505632ec76 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -22,6 +22,7 @@
#include <reset.h>
#include <arch/cpu.h>
+#include <cbmem.h>
#include "sb700.h"
#include "smbus.c"
@@ -40,6 +41,33 @@ static u8 pmio_read(u8 reg)
return inb(PM_INDEX + 1);
}
+static void sb700_acpi_init(void) {
+ pmio_write(0x20, ACPI_PM_EVT_BLK & 0xFF);
+ pmio_write(0x21, ACPI_PM_EVT_BLK >> 8);
+ pmio_write(0x22, ACPI_PM1_CNT_BLK & 0xFF);
+ pmio_write(0x23, ACPI_PM1_CNT_BLK >> 8);
+ pmio_write(0x24, ACPI_PM_TMR_BLK & 0xFF);
+ pmio_write(0x25, ACPI_PM_TMR_BLK >> 8);
+ pmio_write(0x28, ACPI_GPE0_BLK & 0xFF);
+ pmio_write(0x29, ACPI_GPE0_BLK >> 8);
+
+ /* CpuControl is in \_PR.CPU0, 6 bytes */
+ pmio_write(0x26, ACPI_CPU_CONTROL & 0xFF);
+ pmio_write(0x27, ACPI_CPU_CONTROL >> 8);
+
+ pmio_write(0x2A, 0); /* AcpiSmiCmdLo */
+ pmio_write(0x2B, 0); /* AcpiSmiCmdHi */
+
+ pmio_write(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
+ pmio_write(0x2D, ACPI_PMA_CNT_BLK >> 8);
+
+ pmio_write(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
+ * the contents of the PM registers at
+ * index 20-2B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ pmio_write(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+}
+
/* RPR 2.28: Get SB ASIC Revision. */
static u8 set_sb700_revision(void)
{
@@ -588,10 +616,61 @@ static void sb700_early_setup(void)
{
printk(BIOS_INFO, "sb700_early_setup()\n");
sb700_por_init();
+ sb700_acpi_init();
}
static int smbus_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
+
+int s3_save_nvram_early(u32 dword, int size, int nvram_pos) {
+ int i;
+ printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
+
+ for (i = 0; i<size; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ nvram_pos++;
+ }
+
+ return nvram_pos;
+}
+
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+ u32 data = *old_dword;
+ int i;
+ for (i = 0; i<size; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ data &= ~(0xff << (i * 8));
+ data |= inb(BIOSRAM_DATA) << (i *8);
+ nvram_pos++;
+ }
+ *old_dword = data;
+ printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size,
+ nvram_pos-size);
+ return nvram_pos;
+}
+
+#if CONFIG_HAVE_ACPI_RESUME == 1
+static int acpi_is_wakeup_early(void) {
+ u16 tmp;
+ tmp = inw(ACPI_PM1_CNT_BLK);
+ printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
+ return (((tmp & (7 << 10)) >> 10) == 3);
+}
+#endif
+
+struct cbmem_entry *get_cbmem_toc(void) {
+ uint32_t xdata = 0;
+ int xnvram_pos = 0xfc, xi;
+ for (xi = 0; xi<4; xi++) {
+ outb(xnvram_pos, BIOSRAM_INDEX);
+ xdata &= ~(0xff << (xi * 8));
+ xdata |= inb(BIOSRAM_DATA) << (xi *8);
+ xnvram_pos++;
+ }
+ return (struct cbmem_entry *) xdata;
+}
+
#endif
diff --git a/src/southbridge/amd/sb700/fadt.c b/src/southbridge/amd/sb700/fadt.c
index b8004844fb..b75e8793b1 100644
--- a/src/southbridge/amd/sb700/fadt.c
+++ b/src/southbridge/amd/sb700/fadt.c
@@ -55,33 +55,6 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
-
- pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
-
- /* CpuControl is in \_PR.CPU0, 6 bytes */
- pm_iowrite(0x26, ACPI_CPU_CONTROL & 0xFF);
- pm_iowrite(0x27, ACPI_CPU_CONTROL >> 8);
-
- pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
-
- pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
-
- pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 20-2B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
- pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
-
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
fadt->pm1b_evt_blk = 0x0000;
fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index a3a50c6c9b..c073230821 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -28,6 +28,7 @@
#include <bitops.h>
#include <arch/io.h>
#include <arch/ioapic.h>
+#include <cbmem.h>
#include "sb700.h"
static void lpc_init(device_t dev)
@@ -63,6 +64,27 @@ static void lpc_init(device_t dev)
byte = pci_read_config8(dev, 0x78);
byte &= ~(1 << 1);
pci_write_config8(dev, 0x78, byte);
+
+ /* hack, but the whole sb700 startup lacks any device which
+ is doing the acpi init */
+#if CONFIG_HAVE_ACPI_RESUME == 1
+ {
+ extern u8 acpi_slp_type;
+ u16 tmp = inw(ACPI_PM1_CNT_BLK);
+ acpi_slp_type = ((tmp & (7 << 10)) >> 10);
+ printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type);
+ }
+#endif
+}
+
+void set_cbmem_toc(struct cbmem_entry *toc) {
+ u32 dword = (u32) toc;
+ int nvram_pos = 0xfc, i;
+ for (i = 0; i<4; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ nvram_pos++;
+ }
}
static void sb700_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 72a6b202fe..4ab21c8211 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -24,6 +24,8 @@
#include "chip.h"
/* Power management index/data registers */
+#define BIOSRAM_INDEX 0xcd4
+#define BIOSRAM_DATA 0xcd5
#define PM_INDEX 0xcd6
#define PM_DATA 0xcd7
#define PM2_INDEX 0xcd0
@@ -68,5 +70,8 @@ void sb700_setup_sata_phys(struct device *dev);
#endif
+int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
+
void sb700_enable_usbdebug(unsigned int port);
#endif /* SB700_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 23:01:08 +0000