diff options
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/sb700/Kconfig | 15 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/bootblock.c | 3 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/early_setup.c | 99 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/enable_usbdebug.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/lpc.c | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sata.c | 9 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sb700.c | 15 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sb700.h | 14 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sm.c | 118 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/usb.c | 23 | ||||
| -rw-r--r-- | src/southbridge/amd/sp5100/chip.h | 33 |
11 files changed, 283 insertions, 54 deletions
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 49cf476dd2..b4cae56998 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -23,21 +23,26 @@ config SOUTHBRIDGE_AMD_SB700 select HAVE_USBDEBUG select TINY_BOOTBLOCK +config SOUTHBRIDGE_AMD_SP5100 + bool + select IOAPIC + select HAVE_USBDEBUG + select TINY_BOOTBLOCK + config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/sb700/bootblock.c" - depends on SOUTHBRIDGE_AMD_SB700 + depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool default n - depends on SOUTHBRIDGE_AMD_SB700 + depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) config EHCI_BAR hex - default 0xfef00000 if SOUTHBRIDGE_AMD_SB700 + default 0xfef00000 if (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) config EHCI_DEBUG_OFFSET hex - default 0xe0 if SOUTHBRIDGE_AMD_SB700 - + default 0xe0 if (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index bf83823197..377bffc780 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -38,8 +38,7 @@ static void sb700_enable_rom(void) u8 reg8; device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, - PCI_DEVICE_ID_ATI_SB700_LPC), 0); + dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_read_config8(dev, 0x48); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 383b24f577..7345cdeca3 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -43,6 +43,7 @@ static u8 pmio_read(u8 reg) static void sb700_acpi_init(void) { + u16 word; pmio_write(0x20, ACPI_PM_EVT_BLK & 0xFF); pmio_write(0x21, ACPI_PM_EVT_BLK >> 8); pmio_write(0x22, ACPI_PM1_CNT_BLK & 0xFF); @@ -67,6 +68,9 @@ static void sb700_acpi_init(void) * index 20-2B to decode ACPI I/O address. * AcpiSmiEn & SmiCmdEn*/ pmio_write(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + word = inl(ACPI_PM1_CNT_BLK); + word |= 1; + outl(word, ACPI_PM1_CNT_BLK); /* set SCI_EN */ } /* RPR 2.28: Get SB ASIC Revision. */ @@ -125,7 +129,7 @@ static u8 set_sb700_revision(void) * Console output through any port besides 0x3f8 is unsupported. * If you use FWH ROMs, you have to setup IDSEL. ***************************************/ -static void sb700_lpc_init(void) +static void sb7xx_51xx_lpc_init(void) { u8 reg8; u32 reg32; @@ -145,11 +149,25 @@ static void sb700_lpc_init(void) reg32 |= 1 << 20; pci_write_config32(dev, 0x64, reg32); +#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 + post_code(0x66); + dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + reg8 = pci_read_config8(dev, 0xBB); + reg8 |= 1 << 2 | 1 << 3 | 1 << 6 | 1 << 7; + reg8 &= ~(1 << 1); + pci_write_config8(dev, 0xBB, reg8); +#endif + dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ /* Decode port 0x3f8-0x3ff (Serial 0) */ // XXX Serial port decode on LPC is hardcoded to 0x3f8 reg8 = pci_read_config8(dev, 0x44); reg8 |= 1 << 6; +#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_TTYS0_BASE == 0x2f8 + reg8 |= 1 << 7; +#endif +#endif pci_write_config8(dev, 0x44, reg8); /* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/ @@ -171,6 +189,32 @@ static void sb700_lpc_init(void) pci_write_config8(dev, 0x48, reg8); } +void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) +{ + /* TODO: Now assume wio_index=0 */ + device_t dev; + u8 reg8; + + dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + pci_write_config32(dev, 0x64, base); + reg8 = pci_read_config8(dev, 0x48); + reg8 |= 1 << 2; + pci_write_config8(dev, 0x48, reg8); +} + +void sb7xx_51xx_disable_wideio(u8 wio_index) +{ + /* TODO: Now assume wio_index=0 */ + device_t dev; + u8 reg8; + + dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + pci_write_config32(dev, 0x64, 0); + reg8 = pci_read_config8(dev, 0x48); + reg8 &= ~(1 << 2); + pci_write_config8(dev, 0x48, reg8); +} + /* what is its usage? */ static u32 get_sbdn(u32 bus) { @@ -256,7 +300,7 @@ void soft_reset(void) outb(0x06, 0x0cf9); } -void sb700_pci_port80(void) +void sb7xx_51xx_pci_port80(void) { u8 byte; device_t dev; @@ -301,7 +345,7 @@ void sb700_pci_port80(void) pci_write_config8(dev, 0x4A, byte); } -void sb700_lpc_port80(void) +void sb7xx_51xx_lpc_port80(void) { u8 byte; device_t dev; @@ -325,6 +369,9 @@ static void sb700_devices_por_init(void) { device_t dev; u8 byte; +#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 + u32 dword; +#endif printk(BIOS_INFO, "sb700_devices_por_init()\n"); /* SMBus Device, BDF:0-20-0 */ @@ -417,8 +464,25 @@ static void sb700_devices_por_init(void) /* DMA enable */ pci_write_config8(dev, 0x40, 0x04); - /* LPC Sync Timeout */ + /* IO Port Decode Enable */ + pci_write_config8(dev, 0x44, 0xFF); + pci_write_config8(dev, 0x45, 0xFF); + pci_write_config8(dev, 0x46, 0xC3); + pci_write_config8(dev, 0x47, 0xFF); + + // TODO: This has already been done(?) + /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports. + * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f), + * Alternate Super I/O Configuration Port (4e/4f), Wide Generic IO Port (64/65). */ + byte = pci_read_config8(dev, 0x48); + byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */ + byte |= 1 << 6; /* enable for RTC I/O range */ + pci_write_config8(dev, 0x48, byte); pci_write_config8(dev, 0x49, 0xFF); + /* Enable 0x480-0x4bf, 0x4700-0x470B */ + byte = pci_read_config8(dev, 0x4A); + byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */ + pci_write_config8(dev, 0x4A, byte); /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ pci_write_config8(dev, 0x7C, 0x05); @@ -441,6 +505,29 @@ static void sb700_devices_por_init(void) /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */ pci_write_config8(dev, 0x50, 0x01); +#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 + /* SP5100 default SATA mode is RAID5 MODE */ + dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0); + /* Set SATA Operation Mode, Set to IDE mode */ + byte = pci_read_config8(dev, 0x40); + byte |= (1 << 0); + pci_write_config8(dev, 0x40, byte); + + dword = 0x01018f00; + pci_write_config32(dev, 0x8, dword); + + /* set SATA Device ID writable */ + dword = pci_read_config32(dev, 0x40); + dword &= ~(1 << 24); + pci_write_config32(dev, 0x40, dword); + + /* set Device ID accommodate with IDE emulation mode configuration*/ + pci_write_config32(dev, 0x0, 0x43901002); + + /* rpr v2.13 4.17 Reset CPU on Sync Flood */ + abcfg_reg(0x10050, 1 << 2, 1 << 2); +#endif + /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-18-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0); @@ -594,7 +681,7 @@ static void sb700_por_init(void) /* * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration. */ -static void sb700_before_pci_init(void) +static void sb7xx_51xx_before_pci_init(void) { sb700_pci_cfg(); } @@ -602,7 +689,7 @@ static void sb700_before_pci_init(void) /* * This function should be called after enable_sb700_smbus(). */ -static void sb700_early_setup(void) +static void sb7xx_51xx_early_setup(void) { printk(BIOS_INFO, "sb700_early_setup()\n"); sb700_por_init(); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index d74a9bbc9f..b8d584a73c 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -45,7 +45,7 @@ void set_debug_port(unsigned int port) * This code currently only supports the first one, i.e., USB Debug devices * attached to physical USB ports belonging to the first EHCI device. */ -void sb700_enable_usbdebug(unsigned int port) +void sb7xx_51xx_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index fda99d6e38..273aabc128 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -63,6 +63,12 @@ static void lpc_init(device_t dev) /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); +#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 + /* Disable FlowContrl, Always service the request from Host + * whenever there is a request from Host pending + */ + byte &= ~(1 << 0); +#endif pci_write_config8(dev, 0x78, byte); /* hack, but the whole sb700 startup lacks any device which diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 1ad9bdd9df..4838d93658 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -54,7 +54,7 @@ static int sata_drive_detect(int portnum, u16 iobar) } /* This function can be overloaded in mainboard.c */ -void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev) +void __attribute__((weak)) sb7xx_51xx_setup_sata_phys(struct device *dev) { /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ pci_write_config16(dev, 0x86, 0x2c00); @@ -184,12 +184,17 @@ static void sata_init(struct device *dev) /* Program the watchdog counter to 0x10 */ byte = 0x10; pci_write_config8(dev, 0x46, byte); - sb700_setup_sata_phys(dev); + sb7xx_51xx_setup_sata_phys(dev); /* Enable the I/O, MM, BusMaster access for SATA */ byte = pci_read_config8(dev, 0x4); byte |= 7 << 0; pci_write_config8(dev, 0x4, byte); +#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 + /* Master Latency Timer */ + pci_write_config32(dev, 0xC, 0x00004000); +#endif + /* RPR7.7 SATA drive detection. */ /* Use BAR5+0x128,BAR0 for Primary Slave */ /* Use BAR5+0x1A8,BAR0 for Primary Slave */ diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c index 05c855a406..6132d2b7b2 100644 --- a/src/southbridge/amd/sb700/sb700.c +++ b/src/southbridge/amd/sb700/sb700.c @@ -104,7 +104,7 @@ static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos, } } -void sb700_enable(device_t dev) +void sb7xx_51xx_enable(device_t dev) { device_t sm_dev = 0; device_t bus_dev = 0; @@ -118,7 +118,7 @@ void sb700_enable(device_t dev) u32 devfn; - printk(BIOS_DEBUG, "sb700_enable()\n"); + printk(BIOS_DEBUG, "sb7xx_51xx_enable()\n"); /* * 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 @@ -161,7 +161,7 @@ void sb700_enable(device_t dev) } i = (dev->path.pci.devfn) & ~7; - i += (2 << 3); + i += (3 << 3); for (devfn = (0x14 << 3); devfn <= i; devfn += (1 << 3)) { sm_dev = find_sm_dev(dev, devfn); if (sm_dev) @@ -226,7 +226,14 @@ void sb700_enable(device_t dev) } } +#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 +struct chip_operations southbridge_amd_sp5100_ops = { + CHIP_NAME("ATI SP5100") + .enable_dev = sb7xx_51xx_enable, +}; +#else struct chip_operations southbridge_amd_sb700_ops = { CHIP_NAME("ATI SB700") - .enable_dev = sb700_enable, + .enable_dev = sb7xx_51xx_enable, }; +#endif diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index 4ab21c8211..741d244b86 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -35,7 +35,7 @@ #define ACPI_PM_EVT_BLK (SB700_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_CNT_BLK (SB700_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (SB700_ACPI_IO_BASE + 0x0F) /* 1 byte */ +#define ACPI_PMA_CNT_BLK (SB700_ACPI_IO_BASE + 0x0E) /* 1 byte */ #define ACPI_PM_TMR_BLK (SB700_ACPI_IO_BASE + 0x18) /* 4 bytes */ #define ACPI_GPE0_BLK (SB700_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_CPU_CONTROL (SB700_ACPI_IO_BASE + 0x08) /* 6 bytes */ @@ -58,20 +58,22 @@ extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); * The differentiate is 0x28, isn't it? */ #define get_sb700_revision(sm_dev) (pci_read_config8((sm_dev), 0x08) - 0x28) -void sb700_enable(device_t dev); +void sb7xx_51xx_enable(device_t dev); #ifdef __PRE_RAM__ -void sb700_lpc_port80(void); -void sb700_pci_port80(void); +void sb7xx_51xx_lpc_port80(void); +void sb7xx_51xx_pci_port80(void); +void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base); +void sb7xx_51xx_disable_wideio(u8 wio_index); #else #include <device/pci.h> /* allow override in mainboard.c */ -void sb700_setup_sata_phys(struct device *dev); +void sb7xx_51xx_setup_sata_phys(struct device *dev); #endif int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -void sb700_enable_usbdebug(unsigned int port); +void sb7xx_51xx_enable_usbdebug(unsigned int port); #endif /* SB700_H */ diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 69df215f52..7d341df327 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -49,6 +49,7 @@ static void sm_init(device_t dev) { u8 byte; u8 byte_old; + u8 rev; u32 dword; u32 ioapic_base; u32 on; @@ -56,6 +57,7 @@ static void sm_init(device_t dev) printk(BIOS_INFO, "sm_init().\n"); + rev = get_sb700_revision(dev); ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */ /* Don't rename APIC ID */ /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8. @@ -161,6 +163,21 @@ static void sm_init(device_t dev) outb(byte, 0x70); } + /*rpr v2.13 2.22 SMBUS PCI Config */ + byte = pci_read_config8(dev, 0xE1); + if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) { + byte |= 1 << 0; + } + /*Set bit2 to 1, enable Io port 60h read/wrire SMi trapping and + *Io port 64h write Smi trapping. conflict with ps2 keyboard + */ + //byte |= 1 << 2 | 1 << 3 | 1 << 4; + byte |= 1 << 3 | 1 << 4; + pci_write_config8(dev, 0xE1, byte); + + /* 2.5 Enabling Non-Posted Memory Write */ + axindxc_reg(0x10, 1 << 9, 1 << 9); + /* 2.11 IO Trap Settings */ abcfg_reg(0x10090, 1 << 16, 1 << 16); @@ -180,8 +197,17 @@ static void sm_init(device_t dev) /* 4.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */ /* 4.7 Enabling Additional Address Bits Checking in Downstream */ - /* 4.15 IO write and SMI ordering enhancement*/ - abcfg_reg(0x9c, 3 << 0 | 1 << 8, 3 << 0 | 1 << 8); + /* 4.16 IO write and SMI ordering enhancement*/ + abcfg_reg(0x9c, 3 << 0, 3 << 0); + if (REV_SB700_A12 == rev) { + abcfg_reg(0x9c, 1 << 8, 1 << 8); + } else if (rev >= REV_SB700_A14) { + abcfg_reg(0x9c, 1 << 8, 0 << 8); + } + if (REV_SB700_A15 == rev) { + abcfg_reg(0x90, 1 << 21, 1 << 21); + abcfg_reg(0x9c, 1 << 5 | 1 << 9 | 1 << 15, 1 << 5 | 1 << 9 | 1 << 15); + } /* 4.8 Set B-Link Prefetch Mode */ abcfg_reg(0x80, 3 << 17, 3 << 17); @@ -193,6 +219,44 @@ static void sm_init(device_t dev) * Transactions for the K8 Platform (for All Revisions) */ abcfg_reg(0x10090, 1 << 8, 1 << 8); + /* ACPI_SOFT_CLOCK_THROTTLE_PERIOD */ + byte = pm_ioread(0x68); + byte &= ~(3 << 6); + byte |= (2 << 6); /* 224us */ + pm_iowrite(0x68, byte); + + if (REV_SB700_A15 == rev) { + u16 word; + + /* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */ + axindxc_reg(0x02, 1 << 9, 1 << 9); + abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0); + abcfg_reg(0x1009C, 0x00000030, 0x00000030); + abcfg_reg(0x10090, 0x00001E00, 0x00001E00); + + /* rpr v2.13 4.19 Enabling Posted Pass Non-Posted Upstream */ + abcfg_reg(0x58, 0x0000F800, 0x0000E800); + + /* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */ + axindxc_reg(0x02, 1 << 10, 1 << 10); + + /* rpr v2.13 2.38 Unconditional Shutdown */ + byte = pci_read_config8(dev, 0x43); + byte &= ~(1 << 3); + pci_write_config8(dev, 0x43, byte); + + word = pci_read_config16(dev, 0x38); + word |= 1 << 12; + pci_write_config16(dev, 0x38, word); + + byte |= 1 << 3; + pci_write_config8(dev, 0x43, byte); + } + //ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER + byte = pci_read_config8(dev, 0xAE); + byte |= 1 << 5; + pci_write_config8(dev, 0xAE, byte); + /* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */ /* 4.12: Enabling AB and BIF Clock Gating */ abcfg_reg(0x10054, 0xFFFF0000, 0x1040000); @@ -292,20 +356,10 @@ static struct smbus_bus_operations lops_smbus_bus = { static void sb700_sm_read_resources(device_t dev) { struct resource *res; - u8 byte; - - /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */ - byte = pm_ioread(0x55); - byte |= 1 << 7; - pm_iowrite(0x55, byte); /* Get the normal pci resources of this device */ /* pci_dev_read_resources(dev); */ - byte = pm_ioread(0x55); - byte &= ~(1 << 7); - pm_iowrite(0x55, byte); - /* apic */ res = new_resource(dev, 0x74); res->base = IO_APIC_ADDR; @@ -315,15 +369,15 @@ static void sb700_sm_read_resources(device_t dev) res->gran = 8; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED; - #if 0 /* Linux ACPI crashes when it is 1. For late debugging. */ - res = new_resource(dev, 0x14); /* TODO: hpet */ + /* Linux ACPI crashes when it is 1. For late debugging. */ + res = new_resource(dev, 0xB4); /* TODO: test hpet */ res->base = 0xfed00000; /* reset hpet to widely accepted address */ res->size = 0x400; res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ res->align = 8; res->gran = 8; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED; - #endif + /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */ /* smbus */ @@ -344,18 +398,34 @@ static void sb700_sm_set_resources(struct device *dev) u8 byte; pci_dev_set_resources(dev); - - /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */ - byte = pm_ioread(0x52); - byte |= 1 << 6; - pm_iowrite(0x52, byte); - res = find_resource(dev, 0x74); pci_write_config32(dev, 0x74, res->base | 1 << 3); -#if 0 /* TODO:hpet */ - res = find_resource(dev, 0x14); - pci_write_config32(dev, 0x14, res->base); + + /* TODO: test hpet */ +#if 0 //rrg-2.0.3 shows BAR1 not used + /* Make SMBUS BAR1(HPET base at offset 14h) visible */ + byte = pci_read_config8(dev, 0x43); + byte &= ~(1 << 3); + pci_write_config8(dev, 0x43, byte); #endif + + res = find_resource(dev, 0xB4); + /* Program HPET BAR Address */ + pci_write_config32(dev, 0xB4, res->base); + + /* Enable decoding of HPET MMIO, enable HPET MSI */ + byte = pci_read_config8(dev, 0x43); + //byte |= (1 << 3); // Make SMBus Bar1 invisible + //byte |= ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); + byte |= (1 << 4); + pci_write_config8(dev, 0x43, byte); + + /* Enable HPET irq */ + byte = pci_read_config8(dev, 0x65); + byte |= (1 << 2); + pci_write_config8(dev, 0x65, byte); + /* TODO: End of test hpet */ + res = find_resource(dev, 0x90); pci_write_config32(dev, 0x90, res->base | 1); } diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index 3b3ad584a7..2957dc5aca 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -34,6 +34,7 @@ static void usb_init(struct device *dev) { u8 byte; u16 word; + u32 dword; /* 6.1 Enable OHCI0-4 and EHCI Controllers */ device_t sm_dev; @@ -60,10 +61,21 @@ static void usb_init(struct device *dev) byte |= (1 << 4); pm_iowrite(0x65, byte); + /* USB_ADVANCED_SLEEP_CONTROL */ + byte = pm_ioread(0x95); + byte &= ~(7 << 0); + byte |= 6 << 0; /* Advanced sleep up to 6 uframes */ + pm_iowrite(0x95, byte); + /* RPR 6.10 Disable OHCI MSI Capability. */ word = pci_read_config16(dev, 0x40); word |= (0x3 << 8); pci_write_config16(dev, 0x40, word); + + /* USB-1_OHCI0_Corner Case S3 Wake Up */ + dword = pci_read_config32(dev, 0x50); + dword |= (1 << 16); + pci_write_config32(dev, 0x50, dword); } static void usb_init2(struct device *dev) @@ -99,11 +111,9 @@ static void usb_init2(struct device *dev) /* RPR 6.12 EHCI Advance PHY Power Savings */ /* RPR says it is just for A12. CIMM sets it when it is above A11. */ /* But it makes the linux crash, so we skip it */ - #if 0 dword = pci_read_config32(dev, 0x50); dword |= 1 << 31; pci_write_config32(dev, 0x50, dword); - #endif /* RPR6.13 Enabling Fix for EHCI Controller Driver Yellow Sign Issue */ /* RPR says it is just for A12. CIMx sets it when it is above A11. */ @@ -118,7 +128,6 @@ static void usb_init2(struct device *dev) /* Each step below causes the linux crashes. Leave them here * for future debugging. */ -#if 0 u8 byte; u16 word; @@ -139,6 +148,13 @@ static void usb_init2(struct device *dev) pci_write_config8(dev, 0x50, byte); } + /* SB700_A15, USB-2_EHCI_PID_ERROR_CHECKING */ + if (rev == REV_SB700_A15) { + word = pci_read_config16(dev, 0x50); + word |= (1 << 9); + pci_write_config16(dev, 0x50, word); + } + /* RPR6.20 Async Park Mode. */ /* RPR recommends not to set these bits. */ #if 0 @@ -163,7 +179,6 @@ static void usb_init2(struct device *dev) dword &= ~(1 << 27); /* 6.23 */ } printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword); -#endif } static void usb_set_resources(struct device *dev) diff --git a/src/southbridge/amd/sp5100/chip.h b/src/southbridge/amd/sp5100/chip.h new file mode 100644 index 0000000000..569e511108 --- /dev/null +++ b/src/southbridge/amd/sp5100/chip.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SP5100_CHIP_H +#define SP5100_CHIP_H + +struct southbridge_amd_sp5100_config +{ + u32 ide0_enable : 1; + u32 sata0_enable : 1; + u32 boot_switch_sata_ide : 1; + u32 hda_viddid; +}; +struct chip_operations; +extern struct chip_operations southbridge_amd_sp5100_ops; + +#endif /* SP5100_CHIP_H */ |