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-rw-r--r--src/southbridge/amd/Makefile.inc1
-rw-r--r--src/southbridge/amd/cimx/Kconfig1
-rw-r--r--src/southbridge/amd/cimx/Makefile.inc1
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/Amd.h384
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/AmdSbLib.h175
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/Kconfig54
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/Makefile.inc33
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/SbEarly.h56
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/SbPlatform.h156
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/bootblock.c97
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/cbtypes.h59
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/chip.h42
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/chip_name.c25
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/early.c167
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/late.c477
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/lpc.c179
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/lpc.h30
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/smbus.c270
-rwxr-xr-xsrc/southbridge/amd/cimx/sb900/smbus.h77
19 files changed, 2284 insertions, 0 deletions
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index 0ec5d7077f..6a9a7c1198 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
@@ -13,4 +13,5 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
subdirs-$(CONFIG_AMD_CIMX_SB800) += cimx
+subdirs-$(CONFIG_AMD_CIMX_SB900) += cimx
diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig
index 38fbb49bee..e7e13c16f4 100644
--- a/src/southbridge/amd/cimx/Kconfig
+++ b/src/southbridge/amd/cimx/Kconfig
@@ -18,3 +18,4 @@
#
source src/southbridge/amd/cimx/sb800/Kconfig
+source src/southbridge/amd/cimx/sb900/Kconfig
diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc
index e00a072d6e..421a11c99d 100644
--- a/src/southbridge/amd/cimx/Makefile.inc
+++ b/src/southbridge/amd/cimx/Makefile.inc
@@ -17,3 +17,4 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h
new file mode 100755
index 0000000000..cfb983c2cf
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/Amd.h
@@ -0,0 +1,384 @@
+/*****************************************************************************
+ * AMD Generic Encapsulated Software Architecture */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA/CIMx core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision:$ @e \$Date:$
+ */
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+// AGESA Types and Definitions
+#ifndef NULL
+ #define NULL 0
+#endif
+
+#define LAST_ENTRY 0xFFFFFFFF
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+#define IN
+#define OUT
+
+#ifndef Int16FromChar
+#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
+#endif
+#ifndef Int32FromChar
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+#endif
+
+#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
+
+typedef unsigned int AGESA_STATUS;
+
+#define AGESA_SUCCESS ((AGESA_STATUS) 0x0)
+#define AGESA_ALERT ((AGESA_STATUS) 0x40000000)
+#define AGESA_WARNING ((AGESA_STATUS) 0x40000001)
+#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003)
+#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001)
+#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002)
+#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
+
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr);
+typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+ PreMemHeap = 0, ///< Create heap in cache.
+ PostMemDram, ///< Create heap in memory.
+ ByHost ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+ AccessWidth8 = 1, ///< Access width is 8 bits.
+ AccessWidth16, ///< Access width is 16 bits.
+ AccessWidth32, ///< Access width is 32 bits.
+ AccessWidth64, ///< Access width is 64 bits.
+
+ AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
+ AccessS3SaveWidth16, ///< Save 16 bits data.
+ AccessS3SaveWidth32, ///< Save 32 bits data.
+ AccessS3SaveWidth64, ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+typedef struct _AMD_CONFIG_PARAMS {
+ IN unsigned int ImageBasePtr; ///< The AGESA Image base address.
+ IN unsigned int Func; ///< The service desired, @sa dispatch.h.
+ IN unsigned int AltImageBasePtr; ///< Alternate Image location
+ IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured.
+ union { ///< Callback pointer
+ IN unsigned long long PlaceHolder; ///< Place holder
+ IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
+ } CALLBACK;
+ IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// AGESA Binary module header structure
+typedef struct _AMD_IMAGE_HEADER {
+ IN unsigned int Signature; ///< Binary Signature
+ IN signed char CreatorID[8]; ///< 8 characters ID
+ IN signed char Version[12]; ///< 12 characters version
+ IN unsigned int ModuleInfoOffset; ///< Offset of module
+ IN unsigned int EntryPointAddress; ///< Entry address
+ IN unsigned int ImageBase; ///< Image base
+ IN unsigned int RelocTableOffset; ///< Relocate Table offset
+ IN unsigned int ImageSize; ///< Size
+ IN unsigned short Checksum; ///< Checksum
+ IN unsigned char ImageType; ///< Type
+ IN unsigned char V_Reserved; ///< Reserved
+} AMD_IMAGE_HEADER;
+
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+ IN unsigned int ModuleHeaderSignature; ///< Module signature
+ IN signed char ModuleIdentifier[8]; ///< 8 characters ID
+ IN signed char ModuleVersion[12]; ///< 12 characters version
+ IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher
+ IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link
+} AMD_MODULE_HEADER;
+
+#define FUNC_0 0 // bit-placed for PCI address creation
+#define FUNC_1 1
+#define FUNC_2 2
+#define FUNC_3 3
+#define FUNC_4 4
+#define FUNC_5 5
+#define FUNC_6 6
+#define FUNC_7 7
+
+// SBDFO - Segment Bus Device Function Offset
+// 31:28 Segment (4-bits)
+// 27:20 Bus (8-bits)
+// 19:15 Device (5-bits)
+// 14:12 Function (3-bits)
+// 11:00 Offset (12-bits)
+
+#if 0
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \
+ (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off)))
+#endif
+#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+/*
+/// CPUID data received registers format
+typedef struct _SB_CPUID_DATA {
+ IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX
+ IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX
+ IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX
+ IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX
+} SB_CPUID_DATA;
+*/
+
+#define WARM_RESET 1
+#define COLD_RESET 2 // Cold reset
+#define RESET_CPU 4 // Triggers a CPU reset
+
+/// HT frequency for external callbacks
+typedef enum {
+ HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
+ HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
+ HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
+ HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
+ HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
+ HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
+ HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
+ HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
+ HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
+ HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
+ HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
+ HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
+ HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
+ HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
+ HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
+ HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks
+} HT_FREQUENCIES;
+
+#ifndef BIT0
+ #define BIT0 0x0000000000000001ull
+#endif
+#ifndef BIT1
+ #define BIT1 0x0000000000000002ull
+#endif
+#ifndef BIT2
+ #define BIT2 0x0000000000000004ull
+#endif
+#ifndef BIT3
+ #define BIT3 0x0000000000000008ull
+#endif
+#ifndef BIT4
+ #define BIT4 0x0000000000000010ull
+#endif
+#ifndef BIT5
+ #define BIT5 0x0000000000000020ull
+#endif
+#ifndef BIT6
+ #define BIT6 0x0000000000000040ull
+#endif
+#ifndef BIT7
+ #define BIT7 0x0000000000000080ull
+#endif
+#ifndef BIT8
+ #define BIT8 0x0000000000000100ull
+#endif
+#ifndef BIT9
+ #define BIT9 0x0000000000000200ull
+#endif
+#ifndef BIT10
+ #define BIT10 0x0000000000000400ull
+#endif
+#ifndef BIT11
+ #define BIT11 0x0000000000000800ull
+#endif
+#ifndef BIT12
+ #define BIT12 0x0000000000001000ull
+#endif
+#ifndef BIT13
+ #define BIT13 0x0000000000002000ull
+#endif
+#ifndef BIT14
+ #define BIT14 0x0000000000004000ull
+#endif
+#ifndef BIT15
+ #define BIT15 0x0000000000008000ull
+#endif
+#ifndef BIT16
+ #define BIT16 0x0000000000010000ull
+#endif
+#ifndef BIT17
+ #define BIT17 0x0000000000020000ull
+#endif
+#ifndef BIT18
+ #define BIT18 0x0000000000040000ull
+#endif
+#ifndef BIT19
+ #define BIT19 0x0000000000080000ull
+#endif
+#ifndef BIT20
+ #define BIT20 0x0000000000100000ull
+#endif
+#ifndef BIT21
+ #define BIT21 0x0000000000200000ull
+#endif
+#ifndef BIT22
+ #define BIT22 0x0000000000400000ull
+#endif
+#ifndef BIT23
+ #define BIT23 0x0000000000800000ull
+#endif
+#ifndef BIT24
+ #define BIT24 0x0000000001000000ull
+#endif
+#ifndef BIT25
+ #define BIT25 0x0000000002000000ull
+#endif
+#ifndef BIT26
+ #define BIT26 0x0000000004000000ull
+#endif
+#ifndef BIT27
+ #define BIT27 0x0000000008000000ull
+#endif
+#ifndef BIT28
+ #define BIT28 0x0000000010000000ull
+#endif
+#ifndef BIT29
+ #define BIT29 0x0000000020000000ull
+#endif
+#ifndef BIT30
+ #define BIT30 0x0000000040000000ull
+#endif
+#ifndef BIT31
+ #define BIT31 0x0000000080000000ull
+#endif
+#ifndef BIT32
+ #define BIT32 0x0000000100000000ull
+#endif
+#ifndef BIT33
+ #define BIT33 0x0000000200000000ull
+#endif
+#ifndef BIT34
+ #define BIT34 0x0000000400000000ull
+#endif
+#ifndef BIT35
+ #define BIT35 0x0000000800000000ull
+#endif
+#ifndef BIT36
+ #define BIT36 0x0000001000000000ull
+#endif
+#ifndef BIT37
+ #define BIT37 0x0000002000000000ull
+#endif
+#ifndef BIT38
+ #define BIT38 0x0000004000000000ull
+#endif
+#ifndef BIT39
+ #define BIT39 0x0000008000000000ull
+#endif
+#ifndef BIT40
+ #define BIT40 0x0000010000000000ull
+#endif
+#ifndef BIT41
+ #define BIT41 0x0000020000000000ull
+#endif
+#ifndef BIT42
+ #define BIT42 0x0000040000000000ull
+#endif
+#ifndef BIT43
+ #define BIT43 0x0000080000000000ull
+#endif
+#ifndef BIT44
+ #define BIT44 0x0000100000000000ull
+#endif
+#ifndef BIT45
+ #define BIT45 0x0000200000000000ull
+#endif
+#ifndef BIT46
+ #define BIT46 0x0000400000000000ull
+#endif
+#ifndef BIT47
+ #define BIT47 0x0000800000000000ull
+#endif
+#ifndef BIT48
+ #define BIT48 0x0001000000000000ull
+#endif
+#ifndef BIT49
+ #define BIT49 0x0002000000000000ull
+#endif
+#ifndef BIT50
+ #define BIT50 0x0004000000000000ull
+#endif
+#ifndef BIT51
+ #define BIT51 0x0008000000000000ull
+#endif
+#ifndef BIT52
+ #define BIT52 0x0010000000000000ull
+#endif
+#ifndef BIT53
+ #define BIT53 0x0020000000000000ull
+#endif
+#ifndef BIT54
+ #define BIT54 0x0040000000000000ull
+#endif
+#ifndef BIT55
+ #define BIT55 0x0080000000000000ull
+#endif
+#ifndef BIT56
+ #define BIT56 0x0100000000000000ull
+#endif
+#ifndef BIT57
+ #define BIT57 0x0200000000000000ull
+#endif
+#ifndef BIT58
+ #define BIT58 0x0400000000000000ull
+#endif
+#ifndef BIT59
+ #define BIT59 0x0800000000000000ull
+#endif
+#ifndef BIT60
+ #define BIT60 0x1000000000000000ull
+#endif
+#ifndef BIT61
+ #define BIT61 0x2000000000000000ull
+#endif
+#ifndef BIT62
+ #define BIT62 0x4000000000000000ull
+#endif
+#ifndef BIT63
+ #define BIT63 0x8000000000000000ull
+#endif
+#endif
diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h
new file mode 100755
index 0000000000..a86f24b6fb
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/AmdSbLib.h
@@ -0,0 +1,175 @@
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _AMD_SB_LIB_H_
+#define _AMD_SB_LIB_H_
+
+typedef signed char *va_list;
+#ifndef _INTSIZEOF
+ #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) )
+#endif
+
+// Also support coding convention rules for var arg macros
+#ifndef va_start
+ #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) )
+#endif
+#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) )
+#define va_end(ap) ( ap = (va_list)0 )
+
+
+#pragma pack (push, 1)
+
+#define IMAGE_ALIGN 32*1024
+#define NUM_IMAGE_LOCATION 32
+
+//Entry Point Call
+typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);
+
+//Hook Call
+
+typedef struct _CIMFILEHEADER
+{
+ unsigned int AMDLogo;
+ unsigned long long CreatorID;
+ unsigned int Version1;
+ unsigned int Version2;
+ unsigned int Version3;
+ unsigned int ModuleInfoOffset;
+ unsigned int EntryPoint;
+ unsigned int ImageBase;
+ unsigned int RelocTableOffset;
+ unsigned int ImageSize;
+ unsigned short CheckSum;
+ unsigned char ImageType;
+ unsigned char Reserved2;
+} CIMFILEHEADER;
+
+#ifndef BIT0
+ #define BIT0 (1 << 0)
+#endif
+#ifndef BIT1
+ #define BIT1 (1 << 1)
+#endif
+#ifndef BIT2
+ #define BIT2 (1 << 2)
+#endif
+#ifndef BIT3
+ #define BIT3 (1 << 3)
+#endif
+#ifndef BIT4
+ #define BIT4 (1 << 4)
+#endif
+#ifndef BIT5
+ #define BIT5 (1 << 5)
+#endif
+#ifndef BIT6
+ #define BIT6 (1 << 6)
+#endif
+#ifndef BIT7
+ #define BIT7 (1 << 7)
+#endif
+#ifndef BIT8
+ #define BIT8 (1 << 8)
+#endif
+#ifndef BIT9
+ #define BIT9 (1 << 9)
+#endif
+#ifndef BIT10
+ #define BIT10 (1 << 10)
+#endif
+#ifndef BIT11
+ #define BIT11 (1 << 11)
+#endif
+#ifndef BIT12
+ #define BIT12 (1 << 12)
+#endif
+#ifndef BIT13
+ #define BIT13 (1 << 13)
+#endif
+#ifndef BIT14
+ #define BIT14 (1 << 14)
+#endif
+#ifndef BIT15
+ #define BIT15 (1 << 15)
+#endif
+#ifndef BIT16
+ #define BIT16 (1 << 16)
+#endif
+#ifndef BIT17
+ #define BIT17 (1 << 17)
+#endif
+#ifndef BIT18
+ #define BIT18 (1 << 18)
+#endif
+#ifndef BIT19
+ #define BIT19 (1 << 19)
+#endif
+#ifndef BIT20
+ #define BIT20 (1 << 20)
+#endif
+#ifndef BIT21
+ #define BIT21 (1 << 21)
+#endif
+#ifndef BIT22
+ #define BIT22 (1 << 22)
+#endif
+#ifndef BIT23
+ #define BIT23 (1 << 23)
+#endif
+#ifndef BIT24
+ #define BIT24 (1 << 24)
+#endif
+#ifndef BIT25
+ #define BIT25 (1 << 25)
+#endif
+#ifndef BIT26
+ #define BIT26 (1 << 26)
+#endif
+#ifndef BIT27
+ #define BIT27 (1 << 27)
+#endif
+#ifndef BIT28
+ #define BIT28 (1 << 28)
+#endif
+#ifndef BIT29
+ #define BIT29 (1 << 29)
+#endif
+#ifndef BIT30
+ #define BIT30 (1 << 30)
+#endif
+#ifndef BIT31
+ #define BIT31 (1 << 31)
+#endif
+
+#pragma pack (pop)
+
+typedef enum
+{
+ AccWidthUint8 = 0,
+ AccWidthUint16,
+ AccWidthUint32,
+} ACC_WIDTH;
+
+#define S3_SAVE 0x80
+
+#endif
diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig
new file mode 100755
index 0000000000..46f635e755
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -0,0 +1,54 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SOUTHBRIDGE_AMD_CIMX_SB900
+ bool
+ select IOAPIC
+
+if SOUTHBRIDGE_AMD_CIMX_SB900
+config SATA_CONTROLLER_MODE
+ hex
+ default 0x0
+ help
+ 0x0 = Native IDE mode.
+ 0x1 = RAID mode.
+ 0x2 = AHCI mode.
+ 0x3 = Legacy IDE mode.
+ 0x4 = IDE->AHCI mode.
+ 0x5 = AHCI mode as 7804 ID (AMD driver).
+ 0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
+
+config PCIB_ENABLE
+ bool
+ default n
+ help
+ n = Disable PCI Bridge Device 14 Function 4.
+ y = Enable PCI Bridge Device 14 Function 4.
+
+config ACPI_SCI_IRQ
+ hex
+ default 0x9
+ help
+ Set SCI IRQ to 9.
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+ string
+ default "southbridge/amd/cimx/sb900/bootblock.c"
+endif #SOUTHBRIDGE_AMD_CIMX_SB900
+
diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc
new file mode 100755
index 0000000000..17618f9747
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/Makefile.inc
@@ -0,0 +1,33 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+subdirs-$(CONFIG_AMD_CIMX_SB900) += ../../../../../src/vendorcode/amd/cimx/sb900
+
+# SB900 Platform Files
+
+romstage-y += early.c
+romstage-y += smbus.c
+
+ramstage-y += late.c
+ramstage-y += early.c
+
+driver-y += smbus.c
+driver-y += lpc.c
+
+
diff --git a/src/southbridge/amd/cimx/sb900/SbEarly.h b/src/southbridge/amd/cimx/sb900/SbEarly.h
new file mode 100755
index 0000000000..5e2b05cfdc
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/SbEarly.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _CIMX_SB_EARLY_H_
+#define _CIMX_SB_EARLY_H_
+
+#define PM_INDEX 0xcd6
+#define PM_DATA 0xcd7
+
+#define SB900_ACPI_IO_BASE 0x800
+
+#define ACPI_PM_EVT_BLK (SB900_ACPI_IO_BASE + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK (SB900_ACPI_IO_BASE + 0x04) /* 2 bytes */
+#define ACPI_PMA_CNT_BLK (SB900_ACPI_IO_BASE + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK (SB900_ACPI_IO_BASE + 0x08) /* 4 bytes */
+#define ACPI_GPE0_BLK (SB900_ACPI_IO_BASE + 0x20) /* 8 bytes */
+#define ACPI_CPU_CONTROL (SB900_ACPI_IO_BASE + 0x10) /* 6 bytes */
+
+#define REV_SB900_A11 0x11
+#define REV_SB900_A12 0x12
+
+/**
+ * @brief Get SouthBridge device number, called by finalize_node_setup()
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus);
+
+/**
+ * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper.
+ */
+void sb_poweron_init(void);
+void sb_before_pci_init(void);
+
+void sb_After_Pci_Init (void);
+void sb_Mid_Post_Init (void);
+void sb_Late_Post (void);
+
+#endif
diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h
new file mode 100755
index 0000000000..0a2e65a735
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h
@@ -0,0 +1,156 @@
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _AMD_SBPLATFORM_H_
+#define _AMD_SBPLATFORM_H_
+
+//#include "cbtypes.h"
+#ifdef NULL
+ #undef NULL
+#endif
+#define NULL 0
+
+typedef unsigned long long PLACEHOLDER;
+
+#ifndef SBOEM_ACPI_RESTORE_SWSMI
+ #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
+ #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
+#endif
+
+#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
+
+/*
+/// Extended PCI Address
+typedef struct _EXT_PCI_ADDR {
+ UINT32 Reg :16; ///< / PCI Register
+ UINT32 Func:3; ///< / PCI Function
+ UINT32 Dev :5; ///< / PCI Device
+ UINT32 Bus :8; ///< / PCI Address
+} EXT_PCI_ADDR;
+
+/// PCI Address
+typedef union _PCI_ADDR {
+ UINT32 ADDR; ///< / 32 bit Address
+ EXT_PCI_ADDR Addr; ///< / Extended PCI Address
+} PCI_ADDR;
+*/
+#endif
+#define FIXUP_PTR(ptr) ptr
+
+#include "AmdSbLib.h"
+#include "Amd.h"
+#include "Hudson-2.h"
+#include "SbType.h"
+#include "AcpiLib.h"
+#include "SbDef.h"
+#include "AmdSbLib.h"
+#include "SbSubFun.h"
+#include "Oem.h"
+#include "AMD.h"
+#include "SbBiosRamUsage.h"
+#include "EcFan.h"
+
+//------------------------------------------------------------------------------------------------------------------------//
+/**
+ * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over
+ * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
+ * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
+ * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
+ * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
+ * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
+ * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
+ * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
+ * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
+ * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
+ * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
+ * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
+ * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
+ * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
+ * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)
+ * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
+ * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
+ * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
+ * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
+ * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
+ * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
+ * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
+ * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
+ * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
+ * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
+ * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
+ * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
+ */
+#define SB_CIMx_PARAMETER 0x02
+
+// Generic
+#define cimSpreadSpectrumDefault TRUE
+#define cimSpreadSpectrumTypeDefault 0x00 // Normal
+#define cimHpetTimerDefault TRUE
+#define cimHpetMsiDisDefault FALSE // Enable
+#define cimIrConfigDefault 0x00 // Disable
+#define cimSpiFastReadEnableDefault 0x00 // Disable
+#define cimSpiFastReadSpeedDefault 0x00 // NULL
+// GPP/AB Controller
+#define cimNbSbGen2Default TRUE
+#define cimAlinkPhyPllPowerDownDefault TRUE
+#define cimResetCpuOnSyncFloodDefault TRUE
+#define cimGppGen2Default FALSE
+#define cimGppMemWrImproveDefault TRUE
+#define cimGppPortAspmDefault FALSE
+#define cimGppLaneReversalDefault FALSE
+#define cimGppPhyPllPowerDownDefault TRUE
+// USB Controller
+#define cimUsbPhyPowerDownDefault FALSE
+// GEC Controller
+#define cimSBGecDebugBusDefault FALSE
+#define cimSBGecPwrDefault 0x03
+// Sata Controller
+#define cimSataSetMaxGen2Default 0x00
+#define cimSATARefClkSelDefault 0x10
+#define cimSATARefDivSelDefault 0x80
+#define cimSataAggrLinkPmCapDefault TRUE
+#define cimSataPortMultCapDefault TRUE
+#define cimSataPscCapDefault 0x00 // Enable
+#define cimSataSscCapDefault 0x00 // Enable
+#define cimSataFisBasedSwitchingDefault FALSE
+#define cimSataCccSupportDefault FALSE
+#define cimSataClkAutoOffDefault FALSE
+#define cimNativepciesupportDefault FALSE
+// Fusion Related
+#define cimAcDcMsgDefault FALSE
+#define cimTimerTickTrackDefault FALSE
+#define cimClockInterruptTagDefault FALSE
+#define cimOhciTrafficHandingDefault FALSE
+#define cimEhciTrafficHandingDefault FALSE
+#define cimFusionMsgCMultiCoreDefault FALSE
+#define cimFusionMsgCStageDefault FALSE
+#endif // _AMD_SBPLATFORM_H_
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
new file mode 100755
index 0000000000..e04cec0e04
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+
+#if CONFIG_CONSOLE_POST == 1
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+#ifndef CONFIG_TTYS0_DIV
+#if ((115200%CONFIG_TTYS0_BAUD) != 0)
+#error Bad ttys0 baud rate
+#endif
+#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
+#endif // CONFIG_TTYS0_DIV
+
+#define UART_LCS CONFIG_TTYS0_LCS
+
+#endif // CONFIG_CONSOLE_POST == 1
+
+
+static void sb900_enable_rom(void)
+{
+ u32 word;
+ u32 dword;
+ device_t dev;
+
+ dev = PCI_DEV(0, 0x14, 0x03);
+ /* SB900 LPC Bridge 0:20:3:44h.
+ * BIT6: Port Enable for serial port 0x3f8-0x3ff
+ * BIT29: Port Enable for KBC port 0x60 and 0x64
+ * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
+ */
+ dword = pci_io_read_config32(dev, 0x44);
+ //dword |= (1<<6) | (1<<29) | (1<<30) ;
+ /*Turn on all of LPC IO Port decode enable */
+ dword = 0xffffffff;
+ pci_io_write_config32(dev, 0x44, dword);
+
+ /* SB900 LPC Bridge 0:20:3:48h.
+ * BIT0: Port Enable for SuperIO 0x2E-0x2F
+ * BIT1: Port Enable for SuperIO 0x4E-0x4F
+ * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
+ * BIT6: Port Enable for RTC IO 0x70-0x73
+ * BIT21: Port Enable for Port 0x80
+ */
+ dword = pci_io_read_config32(dev, 0x48);
+ dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
+ pci_io_write_config32(dev, 0x48, dword);
+
+ /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+ /* Set the 4MB enable bits */
+ word = pci_io_read_config16(dev, 0x6c);
+ word = 0xFFC0;
+ pci_io_write_config16(dev, 0x6c, word);
+}
+
+static void bootblock_southbridge_init(void)
+{
+ /* Setup the rom access for 2M */
+ sb900_enable_rom();
+}
diff --git a/src/southbridge/amd/cimx/sb900/cbtypes.h b/src/southbridge/amd/cimx/sb900/cbtypes.h
new file mode 100755
index 0000000000..4c97a33ed6
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/cbtypes.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CBTYPES_H_
+#define _CBTYPES_H_
+
+//#include <stdint.h>
+
+typedef signed long long __int64;
+typedef void VOID;
+typedef unsigned int UINTN;
+typedef signed char CHAR8;
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned long long UINT64;
+typedef unsigned char BOOLEAN;
+
+#define DMSG_SB_TRACE 0x02
+#define TRACE(Arguments)
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef VOLATILE
+#define VOLATILE volatile
+#endif
+#ifndef CONST
+#define CONST const
+#endif
+
+#ifndef IN
+#define IN
+#endif
+#ifndef OUT
+#define OUT
+#endif
+
+#endif
diff --git a/src/southbridge/amd/cimx/sb900/chip.h b/src/southbridge/amd/cimx/sb900/chip.h
new file mode 100755
index 0000000000..96afc42736
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/chip.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CIMX_SB900_CHIP_H_
+#define _CIMX_SB900_CHIP_H_
+
+extern struct chip_operations southbridge_amd_cimx_sb900_ops;
+
+/*
+ * configuration set in mainboard/devicetree.cb
+ * boot_switch_sata_ide:
+ * 0 -set SATA as primary, PATA(IDE) as secondary.
+ * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
+ * gpp_configuration - The configuration of General Purpose Port A/B/C/D
+ * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
+ * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
+ * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
+ * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
+ */
+struct southbridge_amd_cimx_sb900_config
+{
+ u32 boot_switch_sata_ide : 1;
+ u8 gpp_configuration;
+};
+
+#endif /* _CIMX_SB900_CHIP_H_ */
diff --git a/src/southbridge/amd/cimx/sb900/chip_name.c b/src/southbridge/amd/cimx/sb900/chip_name.c
new file mode 100755
index 0000000000..dd875dcfd6
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/chip_name.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations southbridge_amd_cimx_sb900_ops = {
+ CHIP_NAME("AMD South Bridge SB900")
+};
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
new file mode 100755
index 0000000000..e09eb29958
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+//#include <config.h>
+#include <stdint.h>
+#include <device/pci_ids.h>
+#include <arch/io.h> /* inl, outl */
+#include <arch/romcc_io.h> /* device_t */
+#include "SbPlatform.h"
+#include "SbEarly.h"
+#include "cfg.h" /*sb900_cimx_config*/
+#include <console/console.h>
+#include <console/loglevel.h>
+#include "smbus.h"
+
+
+/**
+ * @brief Get SouthBridge device number
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus)
+{
+ device_t dev;
+
+ printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - Start.\n");
+ //dev = PCI_DEV(bus, 0x14, 0);
+ dev = pci_locate_device_on_bus(
+ PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB900_SM),
+ bus);
+
+ printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - End.\n");
+ return (dev >> 15) & 0x1f;
+}
+
+
+/**
+ * @brief South Bridge CIMx romstage entry,
+ * wrapper of sbPowerOnInit entry point.
+ */
+void sb_poweron_init(void)
+{
+ AMDSBCFG sb_early_cfg;
+ u8 data;
+
+ printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - Start.\n");
+
+ //Enable/Disable PCI Bridge Device 14 Function 4.
+ outb(0xEA, 0xCD6);
+ data = inb(0xCD7);
+ data &= !BIT0;
+ if(!CONFIG_PCIB_ENABLE) {
+ data |= BIT0;
+ }
+ outb(data, 0xCD7);
+
+ SbPowerOnInit_Config(&sb_early_cfg);
+ //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
+ //AmdSbDispatcher(&sb_early_cfg);
+ //TODO
+ //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
+ // VerifyImage() will fail, LocateImage() take minitues to find the image.
+ sbPowerOnInit(&sb_early_cfg);
+ printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - End.\n");
+}
+
+/**
+ * @brief South Bridge CIMx romstage entry,
+ * wrapper of sbPowerOnInit entry point.
+ */
+void sb_before_pci_init(void)
+{
+ AMDSBCFG sb_early_cfg;
+
+ printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - Start.\n");
+ sb900_cimx_config(&sb_early_cfg);
+ //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
+ //AmdSbDispatcher(&sb_early_cfg);
+ //TODO
+ //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
+ // VerifyImage() will fail, LocateImage() take minitues to find the image.
+ sbBeforePciInit(&sb_early_cfg);
+ printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - End.\n");
+}
+
+void sb_After_Pci_Init(void)
+{
+ AMDSBCFG sb_early_cfg;
+
+ printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - Start.\n");
+ sb900_cimx_config(&sb_early_cfg);
+ //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
+ //AmdSbDispatcher(&sb_early_cfg);
+ //TODO
+ //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
+ // VerifyImage() will fail, LocateImage() take minitues to find the image.
+ sbAfterPciInit(&sb_early_cfg);
+ printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - End.\n");
+}
+
+void sb_Mid_Post_Init(void)
+{
+ AMDSBCFG sb_early_cfg;
+
+ printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n");
+ sb900_cimx_config(&sb_early_cfg);
+ //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
+ //AmdSbDispatcher(&sb_early_cfg);
+ //TODO
+ //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
+ // VerifyImage() will fail, LocateImage() take minitues to find the image.
+ sbMidPostInit(&sb_early_cfg);
+ printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - End.\n");
+}
+
+void sb_Late_Post(void)
+{
+ AMDSBCFG sb_early_cfg;
+ u8 data;
+
+ printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - Start.\n");
+ sb900_cimx_config(&sb_early_cfg);
+ //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
+ //AmdSbDispatcher(&sb_early_cfg);
+ //TODO
+ //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
+ // VerifyImage() will fail, LocateImage() take minitues to find the image.
+ sbLatePost(&sb_early_cfg);
+
+ //Set ACPI SCI IRQ to 0x9.
+ data = CONFIG_ACPI_SCI_IRQ;
+ outb(0x10, 0xC00);
+ outb(data, 0xC01);
+ outb(0x90, 0xC00);
+ outb(data, 0xC01);
+
+ if (data > 0x7) {
+ data = inb(0x4D1);
+ data |= (1 << (CONFIG_ACPI_SCI_IRQ - 8));
+ outb(data, 0x4D1);
+ } else {
+ data = inb(0x4D0);
+ data |= (1 << (CONFIG_ACPI_SCI_IRQ));
+ outb(data, 0x4D0);
+ }
+
+ printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - End.\n");
+}
+
+
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
new file mode 100755
index 0000000000..eb17a33b6d
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -0,0 +1,477 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <device/device.h> /* device_t */
+#include <device/pci.h> /* device_operations */
+#include <device/pci_ids.h>
+#include <device/smbus.h> /* smbus_bus_operations */
+#include <console/console.h> /* printk */
+#include "lpc.h" /* lpc_read_resources */
+#include "SbPlatform.h" /* Platfrom Specific Definitions */
+#include "cfg.h" /* sb900 Cimx configuration */
+#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */
+
+
+/*implement in mainboard.c*/
+//void set_pcie_assert(void);
+//void set_pcie_deassert(void);
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+
+#ifndef _RAMSTAGE_
+#define _RAMSTAGE_
+#endif
+static AMDSBCFG sb_late_cfg; //global, init in sb900_cimx_config
+static AMDSBCFG *sb_config = &sb_late_cfg;
+
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func Southbridge CIMx Function ID.
+ * @param[in] data Southbridge Input Data.
+ * @param[in] sb_config Southbridge configuration structure pointer.
+ *
+ */
+u32 sb900_callout_entry(u32 func, u32 data, void* config)
+{
+ u32 ret = 0;
+
+ printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - Start.\n");
+ switch (func) {
+ case CB_SBGPP_RESET_ASSERT:
+ //set_pcie_assert();
+//- set_pcie_reset();
+ break;
+
+ case CB_SBGPP_RESET_DEASSERT:
+ //set_pcie_deassert();
+//- set_pcie_dereset();
+ break;
+
+//- case IMC_FIRMWARE_FAIL:
+//- break;
+
+ default:
+ break;
+ }
+
+ printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - End.\n");
+ return ret;
+}
+
+
+static struct pci_operations lops_pci = {
+ .set_subsystem = 0,
+};
+
+static void lpc_enable_resources(device_t dev)
+{
+
+ printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - Start.\n");
+ pci_dev_enable_resources(dev);
+ //lpc_enable_childrens_resources(dev);
+ printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - End.\n");
+}
+
+static void lpc_init(device_t dev)
+{
+ printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
+ /* SB Configure HPET base and enable bit */
+//- hpetInit(sb_config, &(sb_config->BuildParameters));
+ printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n");
+}
+
+static struct device_operations lpc_ops = {
+ .read_resources = lpc_read_resources,
+ .set_resources = lpc_set_resources,
+ .enable_resources = lpc_enable_resources,
+ .init = lpc_init,
+ .scan_bus = scan_static_bus,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+ .ops = &lpc_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_LPC,
+};
+
+
+static void sata_enable_resources(struct device *dev)
+{
+ printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - Start.\n");
+//- sataInitAfterPciEnum(sb_config);
+ pci_dev_enable_resources(dev);
+ printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - End.\n");
+}
+
+static void sata_init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - Start.\n");
+ sb_config->StdHeader.Func = SB_MID_POST_INIT;
+//- AmdSbDispatcher(sb_config); //sataInitMidPost only
+//- commonInitLateBoot(sb_config);
+//- sataInitLatePost(sb_config);
+ printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - End.\n");
+}
+
+static struct device_operations sata_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = sata_enable_resources, //pci_dev_enable_resources,
+ .init = sata_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver sata_driver __pci_driver = {
+ .ops = &sata_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+#if (CONFIG_SATA_CONTROLLER_MODE == 0x0 || CONFIG_SATA_CONTROLLER_MODE == 0x3)
+ .device = PCI_DEVICE_ID_ATI_SB900_SATA, //SATA IDE Mode
+#endif
+#if (CONFIG_SATA_CONTROLLER_MODE == 0x2 || CONFIG_SATA_CONTROLLER_MODE == 0x4)
+ .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI, //SATA AHCI Mode
+#endif
+#if (CONFIG_SATA_CONTROLLER_MODE == 0x5 || CONFIG_SATA_CONTROLLER_MODE == 0x6)
+ .device = PCI_DEVICE_ID_ATI_SB900_SATA_AMDAHCI, //SATA AMDAHCI Mode
+#endif
+#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x0)
+ .device = PCI_DEVICE_ID_ATI_SB900_SATA_RAID5, //SATA RAID5 Mode
+#endif
+#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x1)
+ .device = PCI_DEVICE_ID_ATI_SB900_SATA_RAID, //SATA RAID Mode
+#endif
+};
+
+
+#if CONFIG_USBDEBUG
+static void usb_set_resources(struct device *dev)
+{
+ struct resource *res;
+ u32 base;
+ u32 old_debug;
+
+ printk(BIOS_DEBUG, "SB900 - Late.c - usb_set_resources - Start.\n");
+ old_debug = get_ehci_debug();
+ set_ehci_debug(0);
+
+ pci_dev_set_resources(dev);
+
+ res = find_resource(dev, 0x10);
+ set_ehci_debug(old_debug);
+ if (!res)
+ return;
+ base = res->base;
+ set_ehci_base(base);
+ report_resource_stored(dev, res, "");
+ printk(BIOS_DEBUG, "SB900 - Late.c - usb_set_resources - End.\n");
+}
+#endif
+
+static void usb_init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - Start.\n");
+//- usbInitAfterPciInit(sb_config);
+//- commonInitLateBoot(sb_config);
+ printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - End.\n");
+}
+
+static struct device_operations usb_ops = {
+ .read_resources = pci_dev_read_resources,
+#if CONFIG_USBDEBUG
+ .set_resources = usb_set_resources,
+#else
+ .set_resources = pci_dev_set_resources,
+#endif
+ .enable_resources = pci_dev_enable_resources,
+ .init = usb_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+/*
+ * The pci id of usb ctrl 0 and 1 are the same.
+ */
+static const struct pci_driver usb_xhci123_driver __pci_driver = {
+ .ops = &usb_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_USB_16_0, /* XHCI-USB1, XHCI-USB2 */
+};
+
+static const struct pci_driver usb_ohci123_driver __pci_driver = {
+ .ops = &usb_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
+};
+
+static const struct pci_driver usb_ehci123_driver __pci_driver = {
+ .ops = &usb_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
+};
+
+static const struct pci_driver usb_ohci4_driver __pci_driver = {
+ .ops = &usb_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_USB_20_5, /* OHCI-USB4 */
+};
+
+
+static void azalia_init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - Start.\n");
+//- azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio
+ printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - End.\n");
+}
+
+static struct device_operations azalia_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = azalia_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver azalia_driver __pci_driver = {
+ .ops = &azalia_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_HDA,
+};
+
+
+static void gec_init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - Start.\n");
+//- gecInitAfterPciEnum(sb_config);
+//- gecInitLatePost(sb_config);
+ printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - End.\n");
+}
+
+static struct device_operations gec_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = gec_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver gec_driver __pci_driver = {
+ .ops = &gec_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_GEC,
+};
+
+
+static void pcie_init(device_t dev)
+{
+ printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - Start.\n");
+//- sbPcieGppLateInit(sb_config);
+ printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - End.\n");
+}
+
+static struct device_operations pci_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pcie_init,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+ .ops = &pci_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCI,
+};
+
+
+struct device_operations bridge_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pcie_init,
+ .scan_bus = pci_scan_bridge,
+ .enable = 0,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
+};
+
+/* 0:15:0 PCIe PortA */
+static const struct pci_driver PORTA_driver __pci_driver = {
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIEA,
+};
+
+/* 0:15:1 PCIe PortB */
+static const struct pci_driver PORTB_driver __pci_driver = {
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIEB,
+};
+
+/* 0:15:2 PCIe PortC */
+static const struct pci_driver PORTC_driver __pci_driver = {
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIEC,
+};
+
+/* 0:15:3 PCIe PortD */
+static const struct pci_driver PORTD_driver __pci_driver = {
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIED,
+};
+
+
+/**
+ * @brief SB Cimx entry point sbBeforePciInit wrapper
+ */
+static void sb900_enable(device_t dev)
+{
+ u8 gpp_port = 0;
+ struct southbridge_amd_cimx_sb900_config *sb_chip =
+ (struct southbridge_amd_cimx_sb900_config *)(dev->chip_info);
+
+ sb900_cimx_config(sb_config);
+ printk(BIOS_DEBUG, "sb900_enable() ");
+
+ /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
+//- commonInitEarlyBoot(sb_config);
+//- commonInitEarlyPost(sb_config);
+
+ switch (dev->path.pci.devfn) {
+ case (0x10 << 3) | 0: /* 0:10:0 XHCI-USB */
+//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only
+ break;
+
+ case (0x11 << 3) | 0: /* 0:11.0 SATA */
+ if (dev->enabled) {
+ sb_config->SATAMODE.SataMode.SataController = ENABLED;
+ if (1 == sb_chip->boot_switch_sata_ide)
+ sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
+ else if (0 == sb_chip->boot_switch_sata_ide)
+ sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
+ } else {
+ sb_config->SATAMODE.SataMode.SataController = DISABLED;
+ }
+
+//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
+ break;
+
+ case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
+ case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
+ case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
+ case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
+ case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
+//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only
+ break;
+
+ case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
+ break;
+
+ case (0x14 << 3) | 1: /* 0:14:1 IDE */
+ if (dev->enabled) {
+ sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
+ } else {
+ sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
+ }
+//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
+ break;
+
+ case (0x14 << 3) | 2: /* 0:14:2 HDA */
+ if (dev->enabled) {
+ if (AZALIA_DISABLE == sb_config->AzaliaController) {
+ sb_config->AzaliaController = AZALIA_AUTO;
+ }
+ printk(BIOS_DEBUG, "hda enabled\n");
+ } else {
+ sb_config->AzaliaController = AZALIA_DISABLE;
+ printk(BIOS_DEBUG, "hda disabled\n");
+ }
+//- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
+ break;
+
+
+ case (0x14 << 3) | 3: /* 0:14:3 LPC */
+ break;
+
+ case (0x14 << 3) | 4: /* 0:14:4 PCI */
+ break;
+
+ case (0x14 << 3) | 6: /* 0:14:6 GEC */
+ if (dev->enabled) {
+ sb_config->GecConfig = 0;
+ printk(BIOS_DEBUG, "gec enabled\n");
+ } else {
+ sb_config->GecConfig = 1;
+ printk(BIOS_DEBUG, "gec disabled\n");
+ }
+//- gecInitBeforePciEnum(sb_config); // Init GEC
+ break;
+
+ case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
+ case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
+ case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
+ case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
+ gpp_port = (dev->path.pci.devfn) & 0x03;
+ if (dev->enabled) {
+ sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
+ } else {
+ sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
+ }
+
+ /*
+ * GPP_CFGMODE_X4000: PortA Lanes[3:0]
+ * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
+ * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
+ * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
+ */
+ if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
+ sb_config->GppLinkConfig = sb_chip->gpp_configuration;
+ }
+
+//- sbPcieGppEarlyInit(sb_config);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Special setting ABCFG registers before PCI emulation. */
+//- abSpecialSetBeforePciEnum(sb_config);
+//- usbDesertPll(sb_config);
+ //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
+ //AmdSbDispatcher(sb_config);
+}
+
+struct chip_operations southbridge_amd_cimx_sb900_ops = {
+ CHIP_NAME("ATI SB900")
+ .enable_dev = sb900_enable,
+};
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c
new file mode 100755
index 0000000000..48bfe36556
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/lpc.c
@@ -0,0 +1,179 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/pci.h>
+#include "lpc.h"
+#include <console/console.h> /* printk */
+
+
+void lpc_read_resources(device_t dev)
+{
+ struct resource *res;
+
+ printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_read_resources - Start.\n");
+ /* Get the normal pci resources of this device */
+ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
+
+ pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
+
+ /* Add an extra subtractive resource for both memory and I/O. */
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+ res->base = 0xff800000;
+ res->size = 0x00800000; /* 8 MB for flash */
+ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, 3); /* IOAPIC */
+ res->base = 0xfec00000;
+ res->size = 0x00001000;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ compact_resources(dev);
+ printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_read_resources - End.\n");
+}
+
+void lpc_set_resources(struct device *dev)
+{
+ struct resource *res;
+
+ printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - Start.\n");
+ pci_dev_set_resources(dev);
+
+ /* Specical case. SPI Base Address. The SpiRomEnable should be set. */
+ res = find_resource(dev, SPIROM_BASE_ADDRESS);
+ pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
+ printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - End.\n");
+}
+
+/**
+ * @brief Enable resources for children devices
+ *
+ * @param dev the device whos children's resources are to be enabled
+ *
+ */
+void lpc_enable_childrens_resources(device_t dev)
+{
+ struct bus *link;
+ u32 reg, reg_x;
+ int var_num = 0;
+ u16 reg_var[3];
+
+ printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_enable_childrens_resources - Start.\n");
+ reg = pci_read_config32(dev, 0x44);
+ reg_x = pci_read_config32(dev, 0x48);
+
+ for (link = dev->link_list; link; link = link->next) {
+ device_t child;
+ for (child = link->children; child;
+ child = child->sibling) {
+ if (child->enabled
+ && (child->path.type == DEVICE_PATH_PNP)) {
+ struct resource *res;
+ for (res = child->resource_list; res; res = res->next) {
+ u32 base, end; /* don't need long long */
+ if (!(res->flags & IORESOURCE_IO))
+ continue;
+ base = res->base;
+ end = resource_end(res);
+/*
+ printk(BIOS_DEBUG, "sb900 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+ dev_path(child), base, end);
+*/
+ switch (base) {
+ case 0x60: /* KB */
+ case 0x64: /* MS */
+ reg |= (1 << 29);
+ break;
+ case 0x3f8: /* COM1 */
+ reg |= (1 << 6);
+ break;
+ case 0x2f8: /* COM2 */
+ reg |= (1 << 7);
+ break;
+ case 0x378: /* Parallal 1 */
+ reg |= (1 << 0);
+ break;
+ case 0x3f0: /* FD0 */
+ reg |= (1 << 26);
+ break;
+ case 0x220: /* Aduio 0 */
+ reg |= (1 << 8);
+ break;
+ case 0x300: /* Midi 0 */
+ reg |= (1 << 18);
+ break;
+ case 0x400:
+ reg_x |= (1 << 16);
+ break;
+ case 0x480:
+ reg_x |= (1 << 17);
+ break;
+ case 0x500:
+ reg_x |= (1 << 18);
+ break;
+ case 0x580:
+ reg_x |= (1 << 19);
+ break;
+ case 0x4700:
+ reg_x |= (1 << 22);
+ break;
+ case 0xfd60:
+ reg_x |= (1 << 23);
+ break;
+ default:
+ if (var_num >= 3)
+ continue; /* only 3 var ; compact them ? */
+ switch (var_num) {
+ case 0:
+ reg_x |= (1 << 2);
+ break;
+ case 1:
+ reg_x |= (1 << 24);
+ break;
+ case 2:
+ reg_x |= (1 << 25);
+ break;
+ }
+ reg_var[var_num++] =
+ base & 0xffff;
+ }
+ }
+ }
+ }
+ }
+ pci_write_config32(dev, 0x44, reg);
+ pci_write_config32(dev, 0x48, reg_x);
+ /* Set WideIO for as many IOs found (fall through is on purpose) */
+ switch (var_num) {
+ case 2:
+ pci_write_config16(dev, 0x90, reg_var[2]);
+ case 1:
+ pci_write_config16(dev, 0x66, reg_var[1]);
+ case 0:
+ //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
+ break;
+ }
+ printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_enable_childrens_resources - End.\n");
+}
diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h
new file mode 100755
index 0000000000..f4d1493fba
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/lpc.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _SB900_LPC_H_
+#define _SB900_LPC_H_
+
+
+#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */
+
+void lpc_read_resources(device_t dev);
+void lpc_set_resources(device_t dev);
+void lpc_enable_childrens_resources(device_t dev);
+
+#endif
diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c
new file mode 100755
index 0000000000..1fbf5ac6c7
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/smbus.c
@@ -0,0 +1,270 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include "smbus.h"
+#include <console/console.h> /* printk */
+
+static inline void smbus_delay(void)
+{
+ outb(inb(0x80), 0x80);
+}
+
+static int smbus_wait_until_ready(u32 smbus_io_base)
+{
+ u32 loops;
+
+ loops = SMBUS_TIMEOUT;
+ do {
+ u8 val;
+ val = inb(smbus_io_base + SMBHSTSTAT);
+ val &= 0x1f;
+ if (val == 0) { /* ready now */
+ return 0;
+ }
+ outb(val, smbus_io_base + SMBHSTSTAT);
+ } while (--loops);
+
+ return -2; /* time out */
+}
+
+static int smbus_wait_until_done(u32 smbus_io_base)
+{
+ u32 loops;
+
+ loops = SMBUS_TIMEOUT;
+ do {
+ u8 val;
+
+ val = inb(smbus_io_base + SMBHSTSTAT);
+ val &= 0x1f; /* mask off reserved bits */
+ if (val & 0x1c) {
+ return -5; /* error */
+ }
+ if (val == 0x02) {
+ outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */
+ return 0;
+ }
+ } while (--loops);
+
+ return -3; /* timeout */
+}
+
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
+{
+ u8 byte;
+
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
+ return -2; /* not ready */
+ }
+
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - Start.\n");
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; /* Clear [4:2] */
+ byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
+ outb(byte, smbus_io_base + SMBHSTCTRL);
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; /* timeout or error */
+ }
+
+ /* read results of transaction */
+ byte = inb(smbus_io_base + SMBHSTCMD);
+
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - End.\n");
+ return byte;
+}
+
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
+{
+ u8 byte;
+
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
+ return -2; /* not ready */
+ }
+
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - Start.\n");
+ /* set the command... */
+ outb(val, smbus_io_base + SMBHSTCMD);
+
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; /* Clear [4:2] */
+ byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
+ outb(byte, smbus_io_base + SMBHSTCTRL);
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; /* timeout or error */
+ }
+
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - End.\n");
+ return 0;
+}
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
+{
+ u8 byte;
+
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
+ return -2; /* not ready */
+ }
+
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - Start.\n");
+ /* set the command/address... */
+ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; /* Clear [4:2] */
+ byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
+ outb(byte, smbus_io_base + SMBHSTCTRL);
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; /* timeout or error */
+ }
+
+ /* read results of transaction */
+ byte = inb(smbus_io_base + SMBHSTDAT0);
+
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - End.\n");
+ return byte;
+}
+
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
+{
+ u8 byte;
+
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
+ return -2; /* not ready */
+ }
+
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - Start.\n");
+ /* set the command/address... */
+ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+ /* output value */
+ outb(val, smbus_io_base + SMBHSTDAT0);
+
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; /* Clear [4:2] */
+ byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
+ outb(byte, smbus_io_base + SMBHSTCTRL);
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; /* timeout or error */
+ }
+
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - End.\n");
+ return 0;
+}
+
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - Start.\n");
+ outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
+ tmp = inl(AB_DATA);
+ /* rpr 4.2
+ * For certain revisions of the chip, the ABCFG registers,
+ * with an address of 0x100NN (where 'N' is any hexadecimal
+ * number), require an extra programming step.*/
+ outl(0, AB_INDX);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
+ outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
+ outl(tmp, AB_DATA);
+ outl(0, AB_INDX);
+ printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - End.\n");
+}
+
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - Start.\n");
+ outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
+ tmp = inl(AB_DATA);
+ /* rpr 4.2
+ * For certain revisions of the chip, the ABCFG registers,
+ * with an address of 0x100NN (where 'N' is any hexadecimal
+ * number), require an extra programming step.*/
+ outl(0, AB_INDX);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
+ outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
+ outl(tmp, AB_DATA);
+ outl(0, AB_INDX);
+ printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - End.\n");
+}
+
+/* space = 0: AX_INDXC, AX_DATAC
+ * space = 1: AX_INDXP, AX_DATAP
+ */
+void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ printk(BIOS_INFO, "SB900 - Smbus.c - alink_ax_indx - Start.\n");
+ /* read axindc to tmp */
+ outl(space << 29 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(0, AB_INDX);
+ outl(space << 29 | space << 3 | 0x34, AB_INDX);
+ tmp = inl(AB_DATA);
+ outl(0, AB_INDX);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* write tmp */
+ outl(space << 29 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(0, AB_INDX);
+ outl(space << 29 | space << 3 | 0x34, AB_INDX);
+ outl(tmp, AB_DATA);
+ outl(0, AB_INDX);
+ printk(BIOS_INFO, "SB900 - Smbus.c - alink_ax_indx - End.\n");
+}
+
diff --git a/src/southbridge/amd/cimx/sb900/smbus.h b/src/southbridge/amd/cimx/sb900/smbus.h
new file mode 100755
index 0000000000..e6ade1ed48
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/smbus.h
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _SB900_SMBUS_H_
+#define _SB900_SMBUS_H_
+
+//#include <stdint.h>
+
+#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS
+
+#define SMBHSTSTAT 0x0
+#define SMBSLVSTAT 0x1
+#define SMBHSTCTRL 0x2
+#define SMBHSTCMD 0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+
+#define AX_INDXC 0
+#define AX_INDXP 2
+#define AXCFG 4
+#define ABCFG 6
+#define RC_INDXC 1
+#define RC_INDXP 3
+
+#define AB_INDX 0xCD8
+#define AB_DATA (AB_INDX+4)
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#define abcfg_reg(reg, mask, val) \
+ alink_ab_indx((ABCFG), (reg), (mask), (val))
+#define axcfg_reg(reg, mask, val) \
+ alink_ab_indx((AXCFG), (reg), (mask), (val))
+#define axindxc_reg(reg, mask, val) \
+ alink_ax_indx((AX_INDXC), (reg), (mask), (val))
+#define axindxp_reg(reg, mask, val) \
+ alink_ax_indx((AX_INDXP), (reg), (mask), (val))
+#define rcindxc_reg(reg, port, mask, val) \
+ alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
+#define rcindxp_reg(reg, port, mask, val) \
+ alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
+void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
+
+#endif
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