3 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
index 542864a58c..9d40076bea 100644
--- a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
+++ b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
@@ -10,7 +10,7 @@ static unsigned get_sbdn(unsigned bus)
                 PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
                 bus);
 
-        return (dev>>11) & 0x1f;
+        return (dev>>15) & 0x1f;
 
 }
 
diff --git a/src/southbridge/amd/amd8111/amd8111_enable_rom.c b/src/southbridge/amd/amd8111/amd8111_enable_rom.c
index 8c4e4da5da..b8cc5b1a84 100644
--- a/src/southbridge/amd/amd8111/amd8111_enable_rom.c
+++ b/src/southbridge/amd/amd8111/amd8111_enable_rom.c
@@ -6,10 +6,10 @@ static void amd8111_enable_rom(void)
 
 	/* Enable 5MB rom access at 0xFFB00000 - 0xFFFFFFFF */
 	/* Locate the amd8111 */
-	dev = pci_locate_device(PCI_ID(0x1022, 0x7468), 0);
+	dev = pci_io_locate_device(PCI_ID(0x1022, 0x7468), 0);
 
 	/* Set the 5MB enable bits */
-	byte = pci_read_config8(dev, 0x43);
+	byte = pci_io_read_config8(dev, 0x43);
 	byte |= 0xC0;
-	pci_write_config8(dev, 0x43, byte);
+	pci_io_write_config8(dev, 0x43, byte);
 }
diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/amd8111_reset.c
index 8a5f3a5135..e3c061d457 100644
--- a/src/southbridge/amd/amd8111/amd8111_reset.c
+++ b/src/southbridge/amd/amd8111/amd8111_reset.c
@@ -2,9 +2,9 @@
 #include <device/pci_ids.h>
 
 #define PCI_DEV(BUS, DEV, FN) ( \
-	(((BUS) & 0xFF) << 16) | \
-	(((DEV) & 0x1f) << 11) | \
-	(((FN)  & 0x7) << 8))
+	(((BUS) & 0xFFF) << 20) | \
+	(((DEV) & 0x1F) << 15) | \
+	(((FN)  & 0x7) << 12))
 
 #define PCI_ID(VENDOR_ID, DEVICE_ID) \
 	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
@@ -14,7 +14,7 @@ typedef unsigned device_t;
 static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
 {
         unsigned addr;
-        addr = dev | where;
+        addr = (dev>>4) | where;
         outl(0x80000000 | (addr & ~3), 0xCF8);
         outb(value, 0xCFC + (addr & 3));
 }
@@ -22,7 +22,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
 static void pci_write_config32(device_t dev, unsigned where, unsigned value)
 {
 	unsigned addr;
-        addr = dev | where;
+        addr = (dev>>4) | where;
         outl(0x80000000 | (addr & ~3), 0xCF8);
         outl(value, 0xCFC);
 }
@@ -30,7 +30,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
 static unsigned pci_read_config32(device_t dev, unsigned where)
 {
 	unsigned addr;
-        addr = dev | where;
+        addr = (dev>>4) | where;
         outl(0x80000000 | (addr & ~3), 0xCF8);
         return inl(0xCFC);
 }
@@ -58,8 +58,8 @@ void hard_reset(void)
 {
 	device_t dev;
 	unsigned bus;
-        unsigned node = 0;
-        unsigned link = get_sblk();
+	unsigned node = 0;
+	unsigned link = get_sblk();
 
 	/* Find the device.
 	 * There can only be one 8111 on a hypertransport chain/bus.