diff options
Diffstat (limited to 'src/southbridge/amd')
37 files changed, 37 insertions, 37 deletions
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index d7317a23a2..db5343dff0 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -20,7 +20,7 @@ * *************************************************************************** * */ - + #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ @@ -112,7 +112,7 @@ typedef union _PCI_ADDR { */ #define SB_CIMx_PARAMETER 0x02 -// Generic +// Generic #define cimSpreadSpectrumDefault TRUE #define cimSpreadSpectrumTypeDefault 0x00 // Normal #define cimHpetTimerDefault TRUE @@ -121,7 +121,7 @@ typedef union _PCI_ADDR { #define cimSpiFastReadEnableDefault 0x01 // Enable #define cimSpiFastReadSpeedDefault 0x01 // 33 MHz #define cimSioHwmPortEnableDefault FALSE -// GPP/AB Controller +// GPP/AB Controller #define cimNbSbGen2Default TRUE #define cimAlinkPhyPllPowerDownDefault TRUE #define cimResetCpuOnSyncFloodDefault TRUE @@ -129,13 +129,13 @@ typedef union _PCI_ADDR { #define cimGppMemWrImproveDefault TRUE #define cimGppPortAspmDefault FALSE #define cimGppLaneReversalDefault FALSE -#define cimGppPhyPllPowerDownDefault TRUE +#define cimGppPhyPllPowerDownDefault TRUE // USB Controller #define cimUsbPhyPowerDownDefault FALSE // GEC Controller #define cimSBGecDebugBusDefault FALSE #define cimSBGecPwrDefault 0x03 -// Sata Controller +// Sata Controller #define cimSataSetMaxGen2Default 0x00 #define cimSATARefClkSelDefault 0x10 #define cimSATARefDivSelDefault 0x80 @@ -143,11 +143,11 @@ typedef union _PCI_ADDR { #define cimSataPortMultCapDefault TRUE #define cimSataPscCapDefault 0x00 // Enable #define cimSataSscCapDefault 0x00 // Enable -#define cimSataFisBasedSwitchingDefault FALSE +#define cimSataFisBasedSwitchingDefault FALSE #define cimSataCccSupportDefault FALSE #define cimSataClkAutoOffDefault FALSE #define cimNativepciesupportDefault FALSE -// Fusion Related +// Fusion Related #define cimAcDcMsgDefault FALSE #define cimTimerTickTrackDefault FALSE #define cimClockInterruptTagDefault FALSE diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 593bd6bfc7..0a339b02f7 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -39,8 +39,8 @@ static void enable_rom(void) pci_io_write_config32(dev, 0x44, dword); /* SB800 LPC Bridge 0:20:3:48h. - * BIT0: Port Enable for SuperIO 0x2E-0x2F - * BIT1: Port Enable for SuperIO 0x4E-0x4F + * BIT0: Port Enable for SuperIO 0x2E-0x2F + * BIT1: Port Enable for SuperIO 0x4E-0x4F * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) * BIT6: Port Enable for RTC IO 0x70-0x73 * BIT21: Port Enable for Port 0x80 diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h index cfb983c2cf..cfb983c2cf 100755..100644 --- a/src/southbridge/amd/cimx/sb900/Amd.h +++ b/src/southbridge/amd/cimx/sb900/Amd.h diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h index a86f24b6fb..a86f24b6fb 100755..100644 --- a/src/southbridge/amd/cimx/sb900/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb900/AmdSbLib.h diff --git a/src/southbridge/amd/cimx/sb900/SbEarly.h b/src/southbridge/amd/cimx/sb900/SbEarly.h index 5e2b05cfdc..5e2b05cfdc 100755..100644 --- a/src/southbridge/amd/cimx/sb900/SbEarly.h +++ b/src/southbridge/amd/cimx/sb900/SbEarly.h diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 3fb45dea64..3fb45dea64 100755..100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index e04cec0e04..e84743bc20 100755..100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -73,8 +73,8 @@ static void sb900_enable_rom(void) pci_io_write_config32(dev, 0x44, dword); /* SB900 LPC Bridge 0:20:3:48h. - * BIT0: Port Enable for SuperIO 0x2E-0x2F - * BIT1: Port Enable for SuperIO 0x4E-0x4F + * BIT0: Port Enable for SuperIO 0x2E-0x2F + * BIT1: Port Enable for SuperIO 0x4E-0x4F * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) * BIT6: Port Enable for RTC IO 0x70-0x73 * BIT21: Port Enable for Port 0x80 @@ -86,7 +86,7 @@ static void sb900_enable_rom(void) /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ /* Set the 4MB enable bits */ word = pci_io_read_config16(dev, 0x6c); - word = 0xFFC0; + word = 0xFFC0; pci_io_write_config16(dev, 0x6c, word); } diff --git a/src/southbridge/amd/cimx/sb900/cbtypes.h b/src/southbridge/amd/cimx/sb900/cbtypes.h index 4c97a33ed6..4c97a33ed6 100755..100644 --- a/src/southbridge/amd/cimx/sb900/cbtypes.h +++ b/src/southbridge/amd/cimx/sb900/cbtypes.h diff --git a/src/southbridge/amd/cimx/sb900/chip.h b/src/southbridge/amd/cimx/sb900/chip.h index 96afc42736..96afc42736 100755..100644 --- a/src/southbridge/amd/cimx/sb900/chip.h +++ b/src/southbridge/amd/cimx/sb900/chip.h diff --git a/src/southbridge/amd/cimx/sb900/chip_name.c b/src/southbridge/amd/cimx/sb900/chip_name.c index dd875dcfd6..dd875dcfd6 100755..100644 --- a/src/southbridge/amd/cimx/sb900/chip_name.c +++ b/src/southbridge/amd/cimx/sb900/chip_name.c diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index bd4fd4fa22..1176ca598c 100755..100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -142,7 +142,7 @@ void sb_Late_Post(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbLatePost(&sb_early_cfg); - + //Set ACPI SCI IRQ to 0x9. data = CONFIG_ACPI_SCI_IRQ; outb(0x10, 0xC00); diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 71c65e31c6..71c65e31c6 100755..100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index 48bfe36556..48bfe36556 100755..100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h index f4d1493fba..f4d1493fba 100755..100644 --- a/src/southbridge/amd/cimx/sb900/lpc.h +++ b/src/southbridge/amd/cimx/sb900/lpc.h diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c index 1fbf5ac6c7..1fbf5ac6c7 100755..100644 --- a/src/southbridge/amd/cimx/sb900/smbus.c +++ b/src/southbridge/amd/cimx/sb900/smbus.c diff --git a/src/southbridge/amd/cimx/sb900/smbus.h b/src/southbridge/amd/cimx/sb900/smbus.h index e6ade1ed48..e6ade1ed48 100755..100644 --- a/src/southbridge/amd/cimx/sb900/smbus.h +++ b/src/southbridge/amd/cimx/sb900/smbus.h diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index dba28e789a..5d816e59f4 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -28,25 +28,25 @@ static void ht_dev_set_resources(device_t dev) { #if CONFIG_EXT_CONF_SUPPORT == 1 - unsigned reg; + unsigned reg; device_t k8_f1; resource_t rbase, rend; u32 base, limit; struct resource *resource; - + printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); - + resource = probe_resource(dev, 0x1C); if (resource) { - set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3 visible + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3 visible set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ - set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program bus range: 255 busses + set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program bus range: 255 busses pci_write_config32(dev, 0x1C, resource->base); /* Enable MMCONFIG decoding. */ set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register. */ set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3 - + // setup resource nonposted in k8 mmio /* Get the base address */ rbase = resource->base; @@ -74,9 +74,9 @@ static void ht_dev_set_resources(device_t dev) limit &= 0x00000048; limit |= ((rend >> 8) & 0xffffff00); limit |= (sblk << 4); - limit |= (1 << 7); + limit |= (1 << 7); printk(BIOS_INFO, "%s <- index %x base %04x limit %04x\n", dev_path(k8_f1), reg, base, limit); - pci_write_config32(k8_f1, reg+4, limit); + pci_write_config32(k8_f1, reg+4, limit); pci_write_config32(k8_f1, reg, base); } } @@ -88,13 +88,13 @@ static void ht_dev_read_resources(device_t dev) { #if CONFIG_EXT_CONF_SUPPORT == 1 struct resource *res; - - printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); - set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3 + + printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3 #endif pci_dev_read_resources(dev); - + #if CONFIG_EXT_CONF_SUPPORT == 1 /* Add an MMCONFIG resource. */ res = new_resource(dev, 0x1C); @@ -104,9 +104,9 @@ static void ht_dev_read_resources(device_t dev) res->gran = log2(res->size); res->limit = 0xffffffffffffffffULL; /* 64bit */ res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED; - + compact_resources(dev); -#endif +#endif } /* for UMA internal graphics */ diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 4bd870bbf2..40a72627e0 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -381,7 +381,7 @@ u32 extractbits(u32 source, int lsb, int msb) int cpuidFamily(void) { u32 baseFamily, extendedFamily, fms; - + fms = cpuid_eax (1); baseFamily = extractbits (fms, 8, 11); extendedFamily = extractbits (fms, 20, 27); diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 3c06d441ce..65a5e2bd2f 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -511,7 +511,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.ucUMAChannelNumber = 2; } } - + // processor type if (is_family0Fh()) vgainfo.ulCPUCapInfo = 3; @@ -539,9 +539,9 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* HT width. */ value = pci_read_config8(nb_dev, 0xcb); - vgainfo.usMinDownStreamHTLinkWidth = - vgainfo.usMaxDownStreamHTLinkWidth = - vgainfo.usMinUpStreamHTLinkWidth = + vgainfo.usMinDownStreamHTLinkWidth = + vgainfo.usMaxDownStreamHTLinkWidth = + vgainfo.usMinUpStreamHTLinkWidth = vgainfo.usMaxUpStreamHTLinkWidth = vgainfo.usMinHTLinkWidth = vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)]; diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index cf6d2dfb1a..717aeab2c6 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -223,7 +223,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) #if (CONFIG_GFXUMA == 1) extern uint64_t uma_memory_size; // bits 7-9: aperture size - // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g + // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7; if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7; if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7; diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c index 7eda2e854c..121e3d7cbf 100644 --- a/src/southbridge/amd/sb600/sata.c +++ b/src/southbridge/amd/sb600/sata.c @@ -123,8 +123,8 @@ static void sata_init(struct device *dev) // no cmos option i = CONFIG_SATA_MODE; } - printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" ); - + printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" ); + dword = pci_read_config32(dev, 0x8); dword &= 0xff0000ff; if (i == SATA_MODE_IDE) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 1f46da2228..1f46da2228 100755..100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c index 4652ca2539..5f415fb9f2 100644 --- a/src/southbridge/amd/sb700/ide.c +++ b/src/southbridge/amd/sb700/ide.c @@ -51,8 +51,8 @@ static void ide_init(struct device *dev) /* set ide as primary, if you want to boot from IDE, you'd better set it * in $vendor/$mainboard/devicetree.cb */ - - + + if (conf->boot_switch_sata_ide == 1) { struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); byte = pci_read_config8(sm_dev, 0xAD); diff --git a/src/southbridge/amd/sb700/pmio.c b/src/southbridge/amd/sb700/pmio.c index baded54ba6..baded54ba6 100755..100644 --- a/src/southbridge/amd/sb700/pmio.c +++ b/src/southbridge/amd/sb700/pmio.c diff --git a/src/southbridge/amd/sb700/pmio.h b/src/southbridge/amd/sb700/pmio.h index 207fdc24ab..207fdc24ab 100755..100644 --- a/src/southbridge/amd/sb700/pmio.h +++ b/src/southbridge/amd/sb700/pmio.h diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index 27ca32eb5e..27ca32eb5e 100755..100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 58b72ad538..58b72ad538 100755..100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index 165c72d52b..165c72d52b 100755..100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 05065b6dbe..05065b6dbe 100755..100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c diff --git a/src/southbridge/amd/sb700/smbus.c b/src/southbridge/amd/sb700/smbus.c index 6edc3de80c..6edc3de80c 100755..100644 --- a/src/southbridge/amd/sb700/smbus.c +++ b/src/southbridge/amd/sb700/smbus.c diff --git a/src/southbridge/amd/sb700/smbus.h b/src/southbridge/amd/sb700/smbus.h index 9ddfc35303..9ddfc35303 100755..100644 --- a/src/southbridge/amd/sb700/smbus.h +++ b/src/southbridge/amd/sb700/smbus.h diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index 793240187f..793240187f 100755..100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index 6692b86d1f..6692b86d1f 100755..100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 50f836e77c..50f836e77c 100755..100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index eebe711cdb..eebe711cdb 100755..100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 14b919de72..14b919de72 100755..100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h index 1b5112b7c2..1b5112b7c2 100755..100644 --- a/src/southbridge/amd/sr5650/sr5650.h +++ b/src/southbridge/amd/sr5650/sr5650.h |