diff options
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/amd8111/bootblock.c | 43 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/enable_rom.c | 42 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/bootblock.c | 52 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/enable_rom.c | 65 |
4 files changed, 90 insertions, 112 deletions
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index a11d1d30f4..3009c0b094 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -1,4 +1,45 @@ -#include "southbridge/amd/amd8111/enable_rom.c" +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux Networx + * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ +static void amd8111_enable_rom(void) +{ + u8 byte; + device_t dev; + + dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_8111_ISA), 0); + + /* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */ + + /* Set the 5MB enable bits. */ + byte = pci_io_read_config8(dev, 0x43); + byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */ + byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */ + pci_io_write_config8(dev, 0x43, byte); +} static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/amd/amd8111/enable_rom.c b/src/southbridge/amd/amd8111/enable_rom.c deleted file mode 100644 index 3e73112b47..0000000000 --- a/src/southbridge/amd/amd8111/enable_rom.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Linux Networx - * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_ids.h> - -/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ -static void amd8111_enable_rom(void) -{ - u8 byte; - device_t dev; - - dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_8111_ISA), 0); - - /* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */ - - /* Set the 5MB enable bits. */ - byte = pci_io_read_config8(dev, 0x43); - byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */ - byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */ - pci_io_write_config8(dev, 0x43, byte); -} diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index a5eb2f2fac..70076227bf 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -1,12 +1,11 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> + * Copyright (C) 2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -18,7 +17,52 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "southbridge/amd/sb600/enable_rom.c" +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* + * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. + * + * Hardware should enable LPC ROM by pin straps. This function does not + * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. + * + * The SB600 power-on default is to map 256K ROM space. + * + * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15. + */ +static void sb600_enable_rom(void) +{ + u8 reg8; + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, + PCI_DEVICE_ID_ATI_SB600_LPC), 0); + + /* Decode variable LPC ROM address ranges 1 and 2. */ + reg8 = pci_read_config8(dev, 0x48); + reg8 |= (1 << 3) | (1 << 4); + pci_write_config8(dev, 0x48, reg8); + + /* LPC ROM address range 1: */ + /* Enable LPC ROM range mirroring start at 0x000e(0000). */ + pci_write_config16(dev, 0x68, 0x000e); + /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ + pci_write_config16(dev, 0x6a, 0x000f); + + /* LPC ROM address range 2: */ + /* + * Enable LPC ROM range start at: + * 0xfff8(0000): 512KB + * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB + */ + pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + /* Enable LPC ROM range end at 0xffff(ffff). */ + pci_write_config16(dev, 0x6e, 0xffff); +} static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/amd/sb600/enable_rom.c b/src/southbridge/amd/sb600/enable_rom.c deleted file mode 100644 index b2668420ce..0000000000 --- a/src/southbridge/amd/sb600/enable_rom.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_ids.h> - -/* - * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. - * - * Hardware should enable LPC ROM by pin straps. This function does not - * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. - * - * The SB600 power-on default is to map 256K ROM space. - * - * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15. - */ -static void sb600_enable_rom(void) -{ - u8 reg8; - device_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, - PCI_DEVICE_ID_ATI_SB600_LPC), 0); - - /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_read_config8(dev, 0x48); - reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(dev, 0x48, reg8); - - /* LPC ROM address range 1: */ - /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_write_config16(dev, 0x68, 0x000e); - /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(dev, 0x6a, 0x000f); - - /* LPC ROM address range 2: */ - /* - * Enable LPC ROM range start at: - * 0xfff8(0000): 512KB - * 0xfff0(0000): 1MB - * 0xffe0(0000): 2MB - * 0xffc0(0000): 4MB - */ - pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ - /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(dev, 0x6e, 0xffff); -} |