14 files changed, 2 insertions, 14 deletions
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index 32b129862d..bb6a54ba42 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -15,7 +15,6 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <device/pci_ids.h>
 
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h
index 165d33f777..bd49e8f05c 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.h
+++ b/src/southbridge/amd/agesa/hudson/hudson.h
@@ -17,7 +17,6 @@
 #ifndef HUDSON_H
 #define HUDSON_H
 
-#include <device/pci_ids.h>
 #include <device/device.h>
 #include "chip.h"
 
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index ce29bf1e77..1754d23d03 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -13,9 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#include "amd8111.h"
+#include <device/pci_ids.h>
 #include <reset.h>
 #include <southbridge/amd/common/reset.h>
+#include "amd8111.h"
 
 unsigned get_sbdn(unsigned bus)
 {
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 922c608a67..27ae4edf47 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -18,7 +18,6 @@
 #define HUDSON_H
 
 #include <types.h>
-#include <device/pci_ids.h>
 #include <device/device.h>
 #include "chip.h"
 
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index 23cd877370..16270d6d89 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -18,7 +18,6 @@
 #include <arch/cpu.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index adf5401bb7..437a62aa87 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -16,7 +16,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <delay.h>
 #include "rs780.h"
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index 3c9393d3e3..36b37ccbe6 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -18,7 +18,6 @@
 #include <arch/acpi.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index e96608eba9..354555fb5c 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -18,7 +18,6 @@
 
 #include <rules.h>
 #include <stdint.h>
-#include <device/pci_ids.h>
 #include "chip.h"
 #include "rev.h"
 
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index e77db5ced9..364fa01c51 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -16,7 +16,6 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <device/pci_ids.h>
 
 #define IO_MEM_PORT_DECODE_ENABLE_5	0x48
 #define IO_MEM_PORT_DECODE_ENABLE_6	0x4a
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 73c0b3740b..0b638f65c4 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -17,7 +17,6 @@
 #ifndef SB700_H
 #define SB700_H
 
-#include <device/pci_ids.h>
 #include "chip.h"
 
 /* Power management index/data registers */
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index e95d4e9ddf..b08d4775c4 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -15,7 +15,6 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <device/pci_ids.h>
 
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index a65c68a94d..3715a3ac1c 100644
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -17,7 +17,6 @@
 #ifndef SB800_H
 #define SB800_H
 
-#include <device/pci_ids.h>
 #include "chip.h"
 
 /* Power management index/data registers */
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 159f3e43eb..f2fd5392fc 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -17,7 +17,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <delay.h>
 #include "sr5650.h"
diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h
index 2e6b728495..06a427987d 100644
--- a/src/southbridge/amd/sr5650/sr5650.h
+++ b/src/southbridge/amd/sr5650/sr5650.h
@@ -19,7 +19,6 @@
 
 #include <stdint.h>
 #include <arch/acpi.h>
-#include <device/pci_ids.h>
 #include "chip.h"
 #include "rev.h"