3 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 8671882a9f..b119df287a 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -57,7 +57,7 @@ static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev,
 	u32 reg_old, reg;
 
 	/* family 10 only, for reg > 0xFF */
-	if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10))
+	if (!CONFIG(NORTHBRIDGE_AMD_AMDFAM10))
 		return;
 
 	reg = reg_old = pci_read_config32(fam10_dev, reg_pos);
@@ -222,7 +222,7 @@ void sr5650_htinit(void)
 		/* Enable Protocol checker */
 		set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC);
 
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
+#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
 		/* HT3 mode, RPR 5.4.3 */
 		set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0);
 
@@ -307,7 +307,7 @@ void fam10_optimization(void)
 	msr_t msr;
 	u32 val;
 
-	if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10))
+	if (!CONFIG(NORTHBRIDGE_AMD_AMDFAM10))
 		return;
 
 	printk(BIOS_INFO, "fam10_optimization()\n");
diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c
index f8db2b8c6d..c08809f4aa 100644
--- a/src/southbridge/amd/sr5650/ht.c
+++ b/src/southbridge/amd/sr5650/ht.c
@@ -155,7 +155,7 @@ static void pcie_init(struct device *dev)
 
 static void sr5690_read_resource(struct device *dev)
 {
-	if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
+	if (CONFIG(EXT_CONF_SUPPORT)) {
 		printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev));
 		set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3);	/* Hide BAR3 */
 	}
@@ -174,7 +174,7 @@ static void sr5690_set_resources(struct device *dev)
 {
 	pci_write_config32(dev, 0xf8, 0x1);	/* Set IOAPIC's index to 1 and make sure no one changes it */
 
-	if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
+	if (CONFIG(EXT_CONF_SUPPORT)) {
 		uint32_t reg;
 		struct device *amd_ht_cfg_dev;
 		struct device *amd_addr_map_dev;
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 9c72750b90..90ca5641cc 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -808,7 +808,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	struct resource *res;
 	resource_t mmconf_base = EXT_CONF_BASE_ADDRESS;
 
-	if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
+	if (CONFIG(EXT_CONF_SUPPORT)) {
 		res = sr5650_retrieve_cpu_mmio_resource();
 		if (res)
 			mmconf_base = res->base;