diff options
Diffstat (limited to 'src/southbridge/amd/sr5650/chip.h')
| -rw-r--r-- | src/southbridge/amd/sr5650/chip.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/amd/sr5650/chip.h b/src/southbridge/amd/sr5650/chip.h index 8a689984a0..d23c614d8f 100644 --- a/src/southbridge/amd/sr5650/chip.h +++ b/src/southbridge/amd/sr5650/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,6 +28,9 @@ struct southbridge_amd_sr5650_config u8 gpp2_configuration; /* The configuration of General Purpose Port. */ u8 gpp3a_configuration; /* The configuration of General Purpose Port. */ u16 port_enable; /* Which port is enabled? GPP(2,3,4,5,6,7,9,10,11,12,13) */ + uint32_t pcie_settling_time; /* How long to wait after link training for PCI-e devices to + * initialize before probing PCI-e busses (in microseconds). + */ }; #endif /* SR5650_CHIP_H */ |