4 files changed, 16 insertions, 22 deletions
diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c
index 22f804ac23..d667143ded 100644
--- a/src/southbridge/amd/sb700/sb700_early_setup.c
+++ b/src/southbridge/amd/sb700/sb700_early_setup.c
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef  _SB700_EARLY_SETUP_C_
-#define  _SB700_EARLY_SETUP_C_
+#ifndef _SB700_EARLY_SETUP_C_
+#define _SB700_EARLY_SETUP_C_
 
 #include <reset.h>
 #include <arch/cpu.h>
@@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg)
 	return inb(PM_INDEX + 1);
 }
 
-/* RPR 2.28 Get SB ASIC Revision.*/
+/* RPR 2.28: Get SB ASIC Revision. */
 static u8 set_sb700_revision(void)
 {
 	device_t dev;
@@ -195,11 +195,11 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 	byte |= 0x03;
 	pmio_write(0x7c, byte);
 
-	/*Must be 0 for K8 platform.*/
+	/* Must be 0 for K8 platform. */
 	byte = pmio_read(0x68);
 	byte &= ~0x01;
 	pmio_write(0x68, byte);
-	/*Must be 0 for K8 platform.*/
+	/* Must be 0 for K8 platform. */
 	byte = pmio_read(0x8d);
 	byte &= ~(1<<6);
 	pmio_write(0x8d, byte);
diff --git a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
index 746cc4306a..06bcab77a3 100644
--- a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
@@ -20,14 +20,12 @@
 #include <usbdebug.h>
 
 #ifndef SB700_DEVN_BASE
-
 #define SB700_DEVN_BASE 0
-
 #endif
 
-#define EHCI_BAR_INDEX 0x10
-#define EHCI_BAR 0xFEF00000
-#define EHCI_DEBUG_OFFSET 0xE0
+#define EHCI_BAR_INDEX		0x10
+#define EHCI_BAR		0xFEF00000
+#define EHCI_DEBUG_OFFSET	0xE0
 
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)
@@ -39,5 +37,5 @@ static void sb700_enable_usbdebug(u32 port)
 	set_debug_port(port);
 	pci_write_config32(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5),
 			   EHCI_BAR_INDEX, EHCI_BAR);
-	pci_write_config8(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5), 0x04, 0x2);	/* mem space enabe */
+	pci_write_config8(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5), 0x04, 0x2);	/* mem space enable */
 }
diff --git a/src/southbridge/amd/sb700/sb700_ide.c b/src/southbridge/amd/sb700/sb700_ide.c
index d56362b03e..08e625492b 100644
--- a/src/southbridge/amd/sb700/sb700_ide.c
+++ b/src/southbridge/amd/sb700/sb700_ide.c
@@ -51,7 +51,7 @@ static void ide_init(struct device *dev)
 	pci_write_config16(dev, 0x4, dword);
 
 	/* set ide as primary, if you want to boot from IDE, you'd better set it
-	 * in mainboard/Config.lb */
+	 * in $vendor/$mainboard/devicetree.cb */
 	if (conf->boot_switch_sata_ide == 1) {
 		byte = pci_read_config8(dev, 0xAD);
 		byte |= 1 << 4;
diff --git a/src/southbridge/amd/sb700/sb700_smbus.c b/src/southbridge/amd/sb700/sb700_smbus.c
index 65e6912568..ee1653df3e 100644
--- a/src/southbridge/amd/sb700/sb700_smbus.c
+++ b/src/southbridge/amd/sb700/sb700_smbus.c
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef  _SB700_SMBUS_C_
-#define  _SB700_SMBUS_C_
+#ifndef _SB700_SMBUS_C_
+#define _SB700_SMBUS_C_
 
 #include "sb700_smbus.h"
 
@@ -90,8 +90,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
 	return byte;
 }
 
-int do_smbus_send_byte(u32 smbus_io_base, u32 device,
-			      u8 val)
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
 {
 	u8 byte;
 
@@ -118,8 +117,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device,
 	return 0;
 }
 
-int do_smbus_read_byte(u32 smbus_io_base, u32 device,
-			      u32 address)
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
 {
 	u8 byte;
 
@@ -149,8 +147,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device,
 	return byte;
 }
 
-int do_smbus_write_byte(u32 smbus_io_base, u32 device,
-			       u32 address, u8 val)
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
 {
 	u8 byte;
 
@@ -180,8 +177,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device,
 	return 0;
 }
 
-static void alink_ab_indx(u32 reg_space, u32 reg_addr,
-			  u32 mask, u32 val)
+static void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
 {
 	u32 tmp;